/** @file
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This module produces the SMM COntrol2 Protocol for QNC
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <Protocol/SmmControl2.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <IntelQNCDxe.h>
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#include <Library/QNCAccessLib.h>
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#include <Uefi/UefiBaseType.h>
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#define EFI_INTERNAL_POINTER 0x00000004
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extern EFI_GUID gEfiEventVirtualAddressChangeGuid;
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/**
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Generates an SMI using the parameters passed in.
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@param This A pointer to an instance of
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EFI_SMM_CONTROL2_PROTOCOL
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@param ArgumentBuffer The argument buffer
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@param ArgumentBufferSize The size of the argument buffer
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@param Periodic TRUE to indicate a periodical SMI
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@param ActivationInterval Interval of the periodical SMI
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@retval EFI_INVALID_PARAMETER Periodic is TRUE or ArgumentBufferSize > 1
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@return Return value from SmmTrigger().
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**/
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EFI_STATUS
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EFIAPI
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Activate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN OUT UINT8 *CommandPort OPTIONAL,
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IN OUT UINT8 *DataPort OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN EFI_SMM_PERIOD ActivationInterval OPTIONAL
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);
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/**
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Clears an SMI.
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@param This Pointer to an instance of EFI_SMM_CONTROL2_PROTOCOL
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@param Periodic TRUE to indicate a periodical SMI
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@return Return value from SmmClear()
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**/
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EFI_STATUS
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EFIAPI
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Deactivate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN BOOLEAN Periodic OPTIONAL
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);
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///
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/// Handle for the SMM Control2 Protocol
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///
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EFI_HANDLE mSmmControl2Handle = NULL;
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///
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/// SMM COntrol2 Protocol instance
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///
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EFI_SMM_CONTROL2_PROTOCOL mSmmControl2 = {
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Activate,
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Deactivate,
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0
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};
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VOID
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EFIAPI
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SmmControlVirtualddressChangeEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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/*++
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Routine Description:
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Fixup internal data pointers so that the services can be called in virtual mode.
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Arguments:
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Event The event registered.
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Context Event context.
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Returns:
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None.
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--*/
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{
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gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl2.Trigger));
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gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl2.Clear));
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}
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/**
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Clear SMI related chipset status and re-enable SMI by setting the EOS bit.
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@retval EFI_SUCCESS The requested operation has been carried out successfully
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@retval EFI_DEVICE_ERROR The EOS bit could not be set.
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**/
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EFI_STATUS
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SmmClear (
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VOID
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)
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{
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UINT16 GPE0BLK_Base;
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//
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// Get GPE0BLK_Base
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//
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GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);
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//
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// Clear the Power Button Override Status Bit, it gates EOS from being set.
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// In QuarkNcSocId - Bit is read only. Handled by external SMC, do nothing.
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//
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//
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// Clear the APM SMI Status Bit
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//
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IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_APM);
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//
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// Set the EOS Bit
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//
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IoOr32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_EOS);
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return EFI_SUCCESS;
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}
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/**
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Generates an SMI using the parameters passed in.
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@param This A pointer to an instance of
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EFI_SMM_CONTROL_PROTOCOL
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@param ArgumentBuffer The argument buffer
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@param ArgumentBufferSize The size of the argument buffer
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@param Periodic TRUE to indicate a periodical SMI
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@param ActivationInterval Interval of the periodical SMI
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@retval EFI_INVALID_PARAMETER Periodic is TRUE or ArgumentBufferSize > 1
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@retval EFI_SUCCESS SMI generated
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**/
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EFI_STATUS
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EFIAPI
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Activate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN OUT UINT8 *CommandPort OPTIONAL,
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IN OUT UINT8 *DataPort OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN EFI_SMM_PERIOD ActivationInterval OPTIONAL
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)
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{
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UINT16 GPE0BLK_Base;
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UINT32 NewValue;
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//
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// Get GPE0BLK_Base
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//
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GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Clear any pending the APM SMI
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//
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if (EFI_ERROR (SmmClear())) {
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return EFI_DEVICE_ERROR;
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}
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//
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// Enable the APMC SMI
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//
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IoOr32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIE, B_QNC_GPE0BLK_SMIE_APM);
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//
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// Enable SMI globally
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//
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NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
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NewValue |= SMI_EN;
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);
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//
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// Set APMC_STS
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//
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if (DataPort == NULL) {
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IoWrite8 (PcdGet16 (PcdSmmDataPort), 0xFF);
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} else {
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IoWrite8 (PcdGet16 (PcdSmmDataPort), *DataPort);
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}
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//
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// Generate the APMC SMI
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//
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if (CommandPort == NULL) {
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IoWrite8 (PcdGet16 (PcdSmmActivationPort), 0xFF);
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} else {
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IoWrite8 (PcdGet16 (PcdSmmActivationPort), *CommandPort);
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}
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return EFI_SUCCESS;
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}
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/**
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Clears an SMI.
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@param This Pointer to an instance of EFI_SMM_CONTROL_PROTOCOL
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@param Periodic TRUE to indicate a periodical SMI
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@return Return value from SmmClear()
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**/
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EFI_STATUS
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EFIAPI
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Deactivate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN BOOLEAN Periodic
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)
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{
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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return SmmClear();
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}
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/**
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This is the constructor for the SMM Control protocol.
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This function installs EFI_SMM_CONTROL2_PROTOCOL.
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@param ImageHandle Handle for the image of this driver
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@param SystemTable Pointer to the EFI System Table
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@retval EFI_UNSUPPORTED There's no Intel ICH on this platform
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@return The status returned from InstallProtocolInterface().
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--*/
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EFI_STATUS
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SmmControl2Init (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_EVENT Event;
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UINT16 PM1BLK_Base;
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UINT16 GPE0BLK_Base;
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BOOLEAN SciEn;
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UINT32 NewValue;
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//
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// Get PM1BLK_Base & GPE0BLK_Base
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//
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PM1BLK_Base = PcdGet16 (PcdPm1blkIoBaseAddress);
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GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);
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//
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// Install our protocol interfaces on the device's handle
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//
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Status = gBS->InstallMultipleProtocolInterfaces (
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&mSmmControl2Handle,
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&gEfiSmmControl2ProtocolGuid, &mSmmControl2,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Determine whether an ACPI OS is present (via the SCI_EN bit)
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//
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SciEn = (BOOLEAN)((IoRead16 (PM1BLK_Base + R_QNC_PM1BLK_PM1C) & B_QNC_PM1BLK_PM1C_SCIEN) != 0);
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if (!SciEn) {
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//
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// Clear any SMIs that double as SCIs (when SCI_EN==0)
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//
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IoWrite16 ((PM1BLK_Base + R_QNC_PM1BLK_PM1S), B_QNC_PM1BLK_PM1S_ALL);
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IoWrite16 ((PM1BLK_Base + R_QNC_PM1BLK_PM1E), 0x00000000);
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IoWrite32 ((PM1BLK_Base + R_QNC_PM1BLK_PM1C), 0x00000000);
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IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_GPE0S), B_QNC_GPE0BLK_GPE0S_ALL);
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IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_GPE0E), 0x00000000);
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}
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//
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// Clear and disable all SMIs that are unaffected by SCI_EN
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// Set EOS
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//
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IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIE), 0x00000000);
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IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), (B_QNC_GPE0BLK_SMIS_EOS + B_QNC_GPE0BLK_SMIS_ALL));
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//
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// Enable SMI globally
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//
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NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
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NewValue |= SMI_EN;
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);
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//
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// Make sure to write this register last -- EOS re-enables SMIs for the QNC
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//
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IoAndThenOr32 (
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GPE0BLK_Base + R_QNC_GPE0BLK_SMIE,
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(UINT32)(~B_QNC_GPE0BLK_SMIE_ALL),
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B_QNC_GPE0BLK_SMIE_APM
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);
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//
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// Make sure EOS bit cleared
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//
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DEBUG_CODE_BEGIN ();
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if (IoRead32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIS) & B_QNC_GPE0BLK_SMIS_EOS) {
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DEBUG ((
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EFI_D_ERROR,
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"******************************************************************************\n"
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"BIG ERROR: SmmControl constructor couldn't properly initialize the ACPI table.\n"
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" SmmControl->Clear will probably hang. \n"
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" NOTE: SCI_EN = %d \n"
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"******************************************************************************\n",
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SciEn
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));
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//
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// If we want the system to stop, then keep the ASSERT(FALSE).
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// Otherwise, comment it out.
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//
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ASSERT (FALSE);
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}
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DEBUG_CODE_END ();
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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SmmControlVirtualddressChangeEvent,
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NULL,
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&gEfiEventVirtualAddressChangeGuid,
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&Event
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);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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