/** @file
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Common definitions and compilation switches for MRC
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __MEMORY_OPTIONS_H
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#define __MEMORY_OPTIONS_H
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#include "core_types.h"
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// MRC COMPILE TIME SWITCHES:
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// ==========================
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//#define MRC_SV // enable some validation opitons
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#if defined (SIM) || defined(EMU)
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#define QUICKSIM // reduce execution time using shorter rd/wr sequences
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#endif
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#define CLT // required for Quark project
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//#define BACKUP_RCVN // enable STATIC timing settings for RCVN (BACKUP_MODE)
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//#define BACKUP_WDQS // enable STATIC timing settings for WDQS (BACKUP_MODE)
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//#define BACKUP_RDQS // enable STATIC timing settings for RDQS (BACKUP_MODE)
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//#define BACKUP_WDQ // enable STATIC timing settings for WDQ (BACKUP_MODE)
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//#define BACKUP_COMPS // enable *COMP overrides (BACKUP_MODE)
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//#define RX_EYE_CHECK // enable the RD_TRAIN eye check
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#define HMC_TEST // enable Host to Memory Clock Alignment
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#define R2R_SHARING // enable multi-rank support via rank2rank sharing
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#define FORCE_16BIT_DDRIO // disable signals not used in 16bit mode of DDRIO
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//
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// Debug support
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//
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#ifdef NDEBUG
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#define DPF if(0) dpf
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#else
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#define DPF dpf
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#endif
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void dpf( uint32_t mask, char_t *bla, ...);
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uint8_t mgetc(void);
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uint8_t mgetch(void);
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// Debug print type
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#define D_ERROR 0x0001
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#define D_INFO 0x0002
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#define D_REGRD 0x0004
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#define D_REGWR 0x0008
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#define D_FCALL 0x0010
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#define D_TRN 0x0020
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#define D_TIME 0x0040
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#define ENTERFN() DPF(D_FCALL, "<%s>\n", __FUNCTION__)
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#define LEAVEFN() DPF(D_FCALL, "</%s>\n", __FUNCTION__)
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#define REPORTFN() DPF(D_FCALL, "<%s/>\n", __FUNCTION__)
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extern uint32_t DpfPrintMask;
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#endif
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