/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <PchAccess.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/MmPciBaseLib.h>
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#include <IncludePrivate/Library/PchResetCommonLib.h>
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EFI_STATUS
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EFIAPI
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PchResetCallback (
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IN PCH_RESET_TYPE PchResetType
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);
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/**
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Initialize an Pch Reset ppi/protocol instance.
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@param[in] PchResetInstance Pointer to PchResetInstance to initialize
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@retval EFI_SUCCESS The protocol instance was properly initialized
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@exception EFI_UNSUPPORTED The PCH is not supported by this module
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**/
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EFI_STATUS
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PchResetConstructor (
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PCH_RESET_INSTANCE *PchResetInstance
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)
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{
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UINTN PmcBaseAddress;
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///
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/// Initialize the Reset protocol instance
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///
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PchResetInstance->Signature = PCH_RESET_SIGNATURE;
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PchResetInstance->Handle = NULL;
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///
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/// Sanity check to ensure PMC ACPI/PM BASE initialization has occurred previously.
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///
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PmcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_PMC,
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PCI_FUNCTION_NUMBER_PCH_PMC
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);
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PchResetInstance->PchPmcBase = PmcBaseAddress;
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PchPwrmBaseGet (&(PchResetInstance->PchPwrmBase));
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ASSERT (PchResetInstance->PchPwrmBase != 0);
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PchAcpiBaseGet (&(PchResetInstance->PchAcpiBase));
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ASSERT (PchResetInstance->PchAcpiBase != 0);
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return EFI_SUCCESS;
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}
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/**
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Execute Pch Reset from the host controller.
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@param[in] PchResetInstance Pointer to PchResetInstance to initialize
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@param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset,
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PowerCycleReset, GlobalReset, GlobalResetWithEc
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER If ResetType is invalid.
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**/
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EFI_STATUS
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PchReset (
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IN PCH_RESET_INSTANCE *PchResetInstance,
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IN PCH_RESET_TYPE PchResetType
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)
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{
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UINTN PmcBaseAddress;
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UINT16 ABase;
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UINT8 OutputData;
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UINT32 Data32;
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UINT16 Data16;
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EFI_STATUS Status;
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PmcBaseAddress = PchResetInstance->PchPmcBase;
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ABase = PchResetInstance->PchAcpiBase;
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switch (PchResetType) {
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case ColdReset:
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IoWrite8 ((UINTN) R_PCH_RST_CNT, (UINT8) V_PCH_RST_CNT_HARDSTARTSTATE);
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OutputData = V_PCH_RST_CNT_FULLRESET;
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break;
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case WarmReset:
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IoWrite8 ((UINTN) R_PCH_RST_CNT, (UINT8) V_PCH_RST_CNT_SOFTSTARTSTATE);
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OutputData = V_PCH_RST_CNT_HARDRESET;
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break;
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case ShutdownReset:
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///
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/// Firstly, ACPI decode must be enabled
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///
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MmioOr8 (
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PmcBaseAddress + R_PCH_PMC_ACPI_CNT,
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(UINT8) (B_PCH_PMC_ACPI_CNT_ACPI_EN)
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);
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///
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/// Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5
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///
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IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_GPE0_EN_127_96), 0);
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///
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/// Secondly, PwrSts register must be cleared
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///
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/// Write a "1" to bit[8] of power button status register at
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/// (PM_BASE + PM1_STS_OFFSET) to clear this bit
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///
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Data16 = B_PCH_SMI_STS_PM1_STS_REG;
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IoWrite16 ((UINTN) (ABase + R_PCH_SMI_STS), Data16);
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///
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/// Finally, transform system into S5 sleep state
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///
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Data32 = IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT));
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Data32 = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);
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IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT), Data32);
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Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;
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IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT), Data32);
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return EFI_SUCCESS;
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case PowerCycleReset:
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case GlobalReset:
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case GlobalResetWithEc:
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///
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/// PCH BIOS Spec Section 4.6 GPIO Reset Requirement
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///
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if ((PchResetType == GlobalReset) || (PchResetType == GlobalResetWithEc)) {
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MmioOr32 (
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PmcBaseAddress + R_PCH_PMC_ETR3,
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(UINT32) (B_PCH_PMC_ETR3_CF9GR)
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);
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}
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OutputData = V_PCH_RST_CNT_FULLRESET;
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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DEBUG ((DEBUG_ERROR, "Resetting the platform (%02x)...\n", OutputData));
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Status = PchResetCallback (PchResetType);
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if ((Status == EFI_SUCCESS) || (Status == EFI_NOT_FOUND)) {
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IoWrite8 ((UINTN) R_PCH_RST_CNT, OutputData);
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///
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/// Waiting for system reset
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///
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CpuDeadLoop ();
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}
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return Status;
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}
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