/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/MmPciBaseLib.h>
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#include <Library/PchPmcLib.h>
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#include <PchAccess.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <PiPei.h>
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#include <Ppi/Spi.h>
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#include <Library/PeiServicesLib.h>
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extern EFI_GUID gPeiSpiPpiGuid;
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/**
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Check whether GbE region is valid
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Check SPI region directly since GbE might be disabled in SW.
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@retval TRUE Gbe Region is valid
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@retval FALSE Gbe Region is invalid
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**/
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BOOLEAN
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PchIsGbeRegionValid (
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VOID
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)
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{
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UINT32 SpiBar;
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SpiBar = MmioRead32 (MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI)
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+ R_PCH_SPI_BAR0) & ~B_PCH_SPI_BAR0_MASK;
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ASSERT (SpiBar != 0);
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if (MmioRead32 (SpiBar + R_PCH_SPI_FREG3_GBE) != B_PCH_SPI_FREGX_BASE_MASK) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Returns GbE over PCIe port number based on a soft strap.
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@return Root port number (1-based)
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@retval 0 GbE over PCIe disabled
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**/
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UINT32
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PchGetGbePortNumber (
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VOID
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)
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{
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UINT32 GbePortSel;
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UINT32 PcieStrapFuse;
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PchPcrRead32 (PID_FIAWM26, R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE, &PcieStrapFuse);
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if ((PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN) == 0) {
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return 0; // GbE disabled
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}
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GbePortSel = (PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL) >> N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL;
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switch (GbePortSel) {
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case 0: return 3 + 1;
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case 1: return 4 + 1;
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case 2: return 5 + 1;
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case 3: return 8 + 1;
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case 4: return 11 + 1;
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}
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DEBUG((DEBUG_ERROR, "Invalid GbE port\n"));
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ASSERT (FALSE);
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return 0;
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}
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/**
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Check whether LAN controller is enabled in the platform.
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@retval TRUE GbE is enabled
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@retval FALSE GbE is disabled
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**/
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BOOLEAN
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PchIsGbePresent (
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VOID
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)
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{
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UINT32 SoftstrapVal;
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EFI_SPI_PROTOCOL *SpiProtocol = NULL;
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EFI_STATUS Status;
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UINTN GbePciBase;
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if (PchIsDwrFlow() == TRUE) {
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return FALSE;
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}
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GbePciBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LAN,
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PCI_FUNCTION_NUMBER_PCH_LAN
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);
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//
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// Check GBE disable strap
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//
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Status = PeiServicesLocatePpi (
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&gPeiSpiPpiGuid,
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0,
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NULL,
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(VOID **) &SpiProtocol
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);
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ASSERT_EFI_ERROR (Status);
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Status = SpiProtocol->ReadPchSoftStrap(SpiProtocol, 0x1DC, 4, &SoftstrapVal);
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if (!EFI_ERROR(Status)) {
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if ((SoftstrapVal & BIT14) == BIT14) {
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return FALSE;
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}
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}
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//
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// Check FIA strap/fuse
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//
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if (PchGetGbePortNumber () == 0) {
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return FALSE;
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}
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//
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// Check GbE NVM
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//
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if (PchIsGbeRegionValid () == FALSE) {
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return FALSE;
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}
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if (MmioRead32 (GbePciBase) == 0xFFFFFFFF) {
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return FALSE;
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}
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return TRUE;
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}
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/**
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Check whether LAN controller is enabled in the platform.
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@deprecated Use PchIsGbePresent instead.
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@retval TRUE GbE is enabled
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@retval FALSE GbE is disabled
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**/
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BOOLEAN
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PchIsGbeAvailable (
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VOID
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)
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{
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return PchIsGbePresent ();
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}
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