/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "GpioLibrary.h"
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/**
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This procedure will handle requirement on SATA DEVSLPx pins.
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@param[in] GpioPad GPIO pad
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@param[in] PadMode GPIO PadMode value
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@param[in out] Dw0Reg Value for PADCFG_DW0 register
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@param[in out] Dw0RegMask Mask of bits which will change in PADCFG_DWO register
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@retval None
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**/
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static
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VOID
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GpioHandleSataDevSlpPad (
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IN GPIO_PAD GpioPad,
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IN UINT32 PadMode,
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IN OUT UINT32 *Dw0Reg,
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IN OUT UINT32 *Dw0RegMask
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)
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{
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//
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// For SATA DEVSLPx pins if used in native 1 mode then ensure that PadRstCfg
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// is set to "00" - Powergood
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//
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if (GpioIsPadASataDevSlpPin (GpioPad, PadMode)) {
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//
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// Set PadRstCfg to Powergood
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//
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*Dw0RegMask |= B_PCH_GPIO_RST_CONF;
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*Dw0Reg |= ((GpioResetPwrGood >> 1) << N_PCH_GPIO_RST_CONF);
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}
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}
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/**
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This SKL PCH specific procedure will initialize multiple SKL PCH GPIO pins
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@param[in] NumberofItem Number of GPIO pads to be updated
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@param[in] GpioInitTableAddress GPIO initialization table
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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static
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EFI_STATUS
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GpioConfigureSklPch (
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IN UINT32 NumberOfItems,
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IN GPIO_INIT_CONFIG *GpioInitTableAddress
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)
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{
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UINT32 Index;
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UINT32 Dw0Reg;
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UINT32 Dw0RegMask;
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UINT32 Dw1Reg;
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UINT32 Dw1RegMask;
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UINT32 PadCfgReg;
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UINT32 HostSoftOwnReg[V_PCH_GPIO_GROUP_MAX];
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UINT32 HostSoftOwnRegMask[V_PCH_GPIO_GROUP_MAX];
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UINT32 GpiGpeEnReg[V_PCH_GPIO_GROUP_MAX];
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UINT32 GpiGpeEnRegMask[V_PCH_GPIO_GROUP_MAX];
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GPIO_GROUP_INFO *GpioGroupInfo;
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UINTN GpioGroupInfoLength;
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GPIO_GROUP GpioGroupOffset;
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UINT32 NumberOfGroups;
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GPIO_PAD_OWN PadOwnVal;
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GPIO_INIT_CONFIG *GpioData;
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GPIO_GROUP Group;
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UINT32 GroupIndex;
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UINT32 PadNumber;
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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PadOwnVal = GpioPadOwnHost;
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ZeroMem (HostSoftOwnReg, sizeof (HostSoftOwnReg));
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ZeroMem (HostSoftOwnRegMask, sizeof (HostSoftOwnRegMask));
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ZeroMem (GpiGpeEnReg, sizeof (GpiGpeEnReg));
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ZeroMem (GpiGpeEnRegMask, sizeof (GpiGpeEnRegMask));
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GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
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GpioGroupOffset = GpioGetLowestGroup ();
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NumberOfGroups = GpioGetNumberOfGroups ();
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for (Index = 0; Index < NumberOfItems; Index ++) {
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Dw0RegMask = 0;
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Dw0Reg = 0;
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Dw1RegMask = 0;
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Dw1Reg = 0;
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GpioData = &GpioInitTableAddress[Index];
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Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
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GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
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PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
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if (GroupIndex >= V_PCH_GPIO_GROUP_MAX) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Invalid Group Index (GroupIndex=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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ASSERT (FALSE);
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continue;
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}
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DEBUG_CODE_BEGIN();
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if (!(((PchSeries == PchH) && (GPIO_GET_CHIPSET_ID(GpioData->GpioPad) == GPIO_SKL_H_CHIPSET_ID)) ||
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((PchSeries == PchLp) && (GPIO_GET_CHIPSET_ID(GpioData->GpioPad) == GPIO_SKL_LP_CHIPSET_ID)))) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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DEBUG_CODE_END();
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//
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// Check if group argument exceeds GPIO group range
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//
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if ((Group < GpioGroupOffset) || (Group >= NumberOfGroups + GpioGroupOffset)) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Check if legal pin number
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//
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if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){
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return EFI_INVALID_PARAMETER;
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}
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if (GpioIsPadLocked (GroupIndex, PadNumber)) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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continue;
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}
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if (DebugCodeEnabled ()) {
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//
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// Check if selected GPIO Pad is not owned by CSME/ISH
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//
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GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
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if (PadOwnVal != GpioPadOwnHost) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
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DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
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continue;
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}
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}
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//
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// Configure Reset Type (PadRstCfg)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.PowerConfig & GPIO_CONF_RESET_MASK) >> GPIO_CONF_RESET_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RST_CONF);
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Dw0Reg |= (((GpioData->GpioConfig.PowerConfig & GPIO_CONF_RESET_MASK) >> (GPIO_CONF_RESET_BIT_POS + 1)) << N_PCH_GPIO_RST_CONF);
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//
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// Configure how interrupt is triggered (RxEvCfg)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> GPIO_CONF_INT_TRIG_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_LVL_EDG);
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Dw0Reg |= (((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> (GPIO_CONF_INT_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG);
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//
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// Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> GPIO_CONF_INT_ROUTE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE));
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Dw0Reg |= (((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> (GPIO_CONF_INT_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE);
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//
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// Configure GPIO direction (GPIORxDis and GPIOTxDis)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.Direction & GPIO_CONF_DIR_MASK) >> GPIO_CONF_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RXDIS | B_PCH_GPIO_TXDIS));
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Dw0Reg |= (((GpioData->GpioConfig.Direction & GPIO_CONF_DIR_MASK) >> (GPIO_CONF_DIR_BIT_POS + 1)) << N_PCH_GPIO_TXDIS);
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//
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// Configure GPIO input inversion (RXINV)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.Direction & GPIO_CONF_INV_MASK) >> GPIO_CONF_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RXINV);
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Dw0Reg |= (((GpioData->GpioConfig.Direction & GPIO_CONF_INV_MASK) >> (GPIO_CONF_INV_BIT_POS + 1)) << N_PCH_GPIO_RXINV);
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//
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// Configure GPIO output state (GPIOTxState)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.OutputState & GPIO_CONF_OUTPUT_MASK) >> GPIO_CONF_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TX_STATE);
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Dw0Reg |= (((GpioData->GpioConfig.OutputState & GPIO_CONF_OUTPUT_MASK) >> (GPIO_CONF_OUTPUT_BIT_POS + 1)) << N_PCH_GPIO_TX_STATE);
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//
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// Configure GPIO RX raw override to '1' (RXRAW1)
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//
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Dw0RegMask |= ((((GpioData->GpioConfig.OtherSettings & GPIO_CONF_RXRAW_MASK) >> GPIO_CONF_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_RAW1);
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Dw0Reg |= (((GpioData->GpioConfig.OtherSettings & GPIO_CONF_RXRAW_MASK) >> (GPIO_CONF_RXRAW_BIT_POS + 1)) << N_PCH_GPIO_RX_RAW1);
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//
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// Configure GPIO Pad Mode (PMode)
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//
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if (((GpioData->GpioPad == GPIO_SKL_H_GPP_B2) ||
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(GpioData->GpioPad == GPIO_SKL_H_GPD7) ||
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(GpioData->GpioPad == GPIO_SKL_H_GPD9)) &&
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(GpioData->GpioConfig.PadMode != GpioPadModeGpio)) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group/Index: %d/%d, Pad: %d cannot be set as NATIVE. Force it to GPIO mode!\n", Group, GroupIndex, PadNumber));
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Dw0RegMask |= B_PCH_GPIO_PAD_MODE;
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Dw0Reg |= ((GpioPadModeGpio >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE);
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} else {
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Dw0RegMask |= ((((GpioData->GpioConfig.PadMode & GPIO_CONF_PAD_MODE_MASK) >> GPIO_CONF_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PAD_MODE);
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Dw0Reg |= (((GpioData->GpioConfig.PadMode & GPIO_CONF_PAD_MODE_MASK) >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE);
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}
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//
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// Configure GPIO termination (Term)
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//
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Dw1RegMask |= ((((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_TERM_MASK) >> GPIO_CONF_TERM_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TERM);
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Dw1Reg |= (((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_TERM_MASK) >> (GPIO_CONF_TERM_BIT_POS + 1)) << N_PCH_GPIO_TERM);
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//
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// Configure GPIO pad tolerance (padtol)
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//
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Dw1RegMask |= ((((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> GPIO_CONF_PADTOL_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PADTOL);
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Dw1Reg |= (((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> (GPIO_CONF_PADTOL_BIT_POS + 1)) << N_PCH_GPIO_PADTOL);
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//
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// Check for additional requirements on setting PADCFG register
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//
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GpioHandleSataDevSlpPad (GpioData->GpioPad, GpioData->GpioConfig.PadMode, &Dw0Reg, &Dw0RegMask);
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//
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// Create PADCFG register offset using group and pad number
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//
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PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset;
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//
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// Write PADCFG DW0 register
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//
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MmioAndThenOr32 (
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(UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg),
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~(UINT32)Dw0RegMask,
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(UINT32)Dw0Reg
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);
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//
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// Write PADCFG DW1 register
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//
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MmioAndThenOr32 (
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(UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4),
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~(UINT32)Dw1RegMask,
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(UINT32)Dw1Reg
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);
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//
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// Update value to be programmed in HOSTSW_OWN register
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//
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HostSoftOwnRegMask[GroupIndex] |= (GpioData->GpioConfig.HostSoftPadOwn & 0x1) << PadNumber;
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HostSoftOwnReg[GroupIndex] |= (GpioData->GpioConfig.HostSoftPadOwn >> 0x1) << PadNumber;
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//
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// Update value to be programmed in GPI_GPE_EN register
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//
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GpiGpeEnRegMask[GroupIndex] |= (GpioData->GpioConfig.InterruptConfig & 0x1) << PadNumber;
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GpiGpeEnReg[GroupIndex] |= ((GpioData->GpioConfig.InterruptConfig & GpioIntSci) >> 3) << PadNumber;
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}
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for (Index = 0; Index < NumberOfGroups; Index++) {
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//
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// Write HOSTSW_OWN registers
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//
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if (GpioGroupInfo[Index].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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(UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[Index].Community, GpioGroupInfo[Index].HostOwnOffset),
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~(UINT32)HostSoftOwnRegMask[Index],
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(UINT32)HostSoftOwnReg[Index]
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);
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}
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//
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// Write GPI_GPE_EN registers
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//
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if (GpioGroupInfo[Index].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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(UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[Index].Community, GpioGroupInfo[Index].GpiGpeEnOffset),
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~(UINT32)GpiGpeEnRegMask[Index],
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(UINT32)GpiGpeEnReg[Index]
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);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This procedure will clear all status bits of any GPIO interrupts.
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@param[in] none
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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static
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EFI_STATUS
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GpioClearAllGpioInterrupts (
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VOID
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)
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{
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GPIO_GROUP Group;
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GPIO_GROUP_INFO *GpioGroupInfo;
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GPIO_GROUP GpioGroupLowest;
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GPIO_GROUP GpioGroupHighest;
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UINT32 GroupIndex;
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UINTN GpioGroupInfoLength;
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GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
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GpioGroupLowest = GpioGetLowestGroup ();
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GpioGroupHighest = GpioGetHighestGroup ();
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for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
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GroupIndex = GpioGetGroupIndexFromGroup (Group);
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//
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// Check if group has GPI IS register
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//
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if (GpioGroupInfo[Group].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all GPI_IS Status bits by writing '1'
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//
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiIsOffset),
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(UINT32)0xFFFFFFFF
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);
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}
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//
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// Check if group has GPI_GPE_STS register
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//
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if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all GPI_GPE_STS Status bits by writing '1'
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//
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeStsOffset),
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(UINT32)0xFFFFFFFF
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);
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}
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//
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// Check if group has SMI_STS register
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//
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if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all SMI_STS Status bits by writing '1'
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//
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiStsOffset),
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(UINT32)0xFFFFFFFF
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);
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}
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//
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// Check if group has NMI_STS register
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//
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if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all NMI_STS Status bits by writing '1'
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//
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].NmiStsOffset),
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(UINT32)0xFFFFFFFF
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);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
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Structure contains fields that can be used to configure each pad.
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Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
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Separate fields could be set to hardware default if it does not matter, except
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GpioPad and PadMode.
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Some GpioPads are configured and switched to native mode by RC, those include:
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SerialIo pins, ISH pins, ClkReq Pins
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@param[in] NumberofItem Number of GPIO pads to be updated
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@param[in] GpioInitTableAddress GPIO initialization table
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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EFI_STATUS
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GpioConfigurePads (
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IN UINT32 NumberOfItems,
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IN GPIO_INIT_CONFIG *GpioInitTableAddress
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)
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{
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EFI_STATUS Status;
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Status = GpioConfigureSklPch (NumberOfItems, GpioInitTableAddress);
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GpioClearAllGpioInterrupts ();
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return Status;
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}
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