/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_HSIO_H_
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#define _PCH_HSIO_H_
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#define PCH_HSIO_SKU_SKL 0x01
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#define PCH_LANE_OWN_COMMON 0x10
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#define PCH_LANE_BDCAST 0x11
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#define PCH_HSIO_LANE_GROUP_NO 0x09
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#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00
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#define PCH_HSIO_LANE_GROUP_PCIE 0x01
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#define PCH_HSIO_LANE_GROUP_DMI 0x02
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#define PCH_HSIO_LANE_GROUP_GBE 0x03
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#define PCH_HSIO_LANE_GROUP_USB3 0x04
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#define PCH_HSIO_LANE_GROUP_SATA 0x05
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#define PCH_HSIO_LANE_GROUP_SSIC 0x06
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#define PCH_MODPHY0_LP_LOS1_LANE_START 0x00
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#define PCH_MODPHY0_LP_LOS1_LANE_END 0x05
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#define PCH_MODPHY1_LP_LOS1_LANE_START 0x06
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#define PCH_MODPHY1_LP_LOS1_LANE_END 0x07
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#define PCH_MODPHY1_LP_LOS2_LANE_START 0x00
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#define PCH_MODPHY1_LP_LOS2_LANE_END 0x01
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#define PCH_MODPHY2_LP_LOS2_LANE_START 0x02
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#define PCH_MODPHY2_LP_LOS2_LANE_END 0x07
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#define PCH_MODPHY1_LOS1_LANE_START 0x00
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#define PCH_MODPHY1_LOS1_LANE_END 0x07
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#define PCH_MODPHY1_LOS2_LANE_START 0x00
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#define PCH_MODPHY1_LOS2_LANE_END 0x01
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#define PCH_MODPHY2_LOS2_LANE_START 0x02
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#define PCH_MODPHY2_LOS2_LANE_END 0x07
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#define PCH_MODPHY2_LOS3_LANE_START 0x00
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#define PCH_MODPHY2_LOS3_LANE_END 0x07
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#define PCH_MODPHY2_LOS4_LANE_START 0x00
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#define PCH_MODPHY2_LOS4_LANE_END 0x01
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/**
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PCH SBI HSIO table data structure
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**/
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typedef struct {
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UINT32 PortId;
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UINT32 Value;
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UINT16 Offset;
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UINT8 LanePhyMode;
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} PCH_SBI_HSIO_TABLE_STRUCT;
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#define PMC_DATA_SBI_CMD_SIZE ((12/sizeof(UINT16))-1)
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#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1)
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// Commands specified command table and processed by the PMC & it's HW accelerator
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typedef enum {
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SendSBIPosted = 0x0, // Perform a SBI Write & wait for result
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SendSBINonPosted, // Perform a SBI Write & ignore return result (Not Supported in HW)
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DoDelay, // PMC Inserts Delay when command detected
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EndStruct = 0x7 // No-op Command indicating end of list
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} PHY_COMMANDS;
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/**
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PCH HSIO PMC XRAM Header
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**/
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typedef struct {
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UINT16 Word0;
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UINT16 Word1;
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UINT16 Word2;
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UINT16 Word3;
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UINT16 Word4;
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UINT16 Word5;
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UINT16 Word6;
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UINT16 Word7;
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UINT16 Word8;
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UINT16 Word9;
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UINT16 Word10;
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UINT16 Word11;
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UINT16 Word12;
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UINT16 Word13;
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UINT16 Word14;
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UINT16 Word15;
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} PCH_SBI_HSIO_HDR_TBL;
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/**
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PCH HSIO PMC XRAM Data
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**/
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typedef struct {
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UINT8 Command : 3;
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UINT8 Size : 5;
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UINT8 Pid;
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UINT8 OpCode; //PrivateControlWrite
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UINT8 Bar; //0
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UINT8 Fbe; //First Byte Enable : 0x0F
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UINT8 Fid; //0
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UINT16 Offset;
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UINT32 Value;
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} PCH_SBI_HSIO_CMD_TBL;
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/**
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PCH HSIO Delay XRAM Data
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**/
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typedef struct {
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UINT8 Command : 3;
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UINT8 Size : 5;
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UINT8 DelayPeriod; //(00h = 1us, 01h = 10us, 02h = 100us, ..., 07h = 10s; others reserved)
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UINT8 DelayCount; //(0 - 255); total delay = Delay period * Delay count
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UINT8 Padding;
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} PCH_DELAY_HSIO_CMD_TBL;
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typedef enum {
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Delay1us = 0x0,
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Delay10us,
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Delay100us,
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Delay1ms,
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Delay10ms,
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Delay100ms,
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Delay1s,
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Delay10s
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} DELAY;
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/**
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PCH PCIE PLL SSC Data
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**/
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#define MAX_PCIE_PLL_SSC_PERCENT 20
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#include <IncludePrivate/PchHHsioBx.h>
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#include <IncludePrivate/PchHHsioDx.h>
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#include <IncludePrivate/PchLpHsioBx.h>
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#include <IncludePrivate/PchLpHsioCx.h>
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#include <IncludePrivate/PchLbgHsioAx.h>
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#include <IncludePrivate/PchLbgHsioBx.h>
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#include <IncludePrivate/PchLbgHsioBx_Ext.h>
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#include <IncludePrivate/PchLbgHsioSx.h>
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#include <IncludePrivate/PchLbgHsioSx_Ext.h>
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#ifdef SKXD_EN
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#include <IncludePrivate/PchLbgHsioBxD.h>
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#include <IncludePrivate/PchLbgHsioBxD_Ext.h>
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#endif // SKXD_EN
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#endif //_PCH_HSIO_H_
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