/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_DCI_H_
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#define _PCH_REGS_DCI_H_
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//
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// DCI PCR Registers
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//
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#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register
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#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock
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#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable
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#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control
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#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register
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#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable
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#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable
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#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable
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#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable
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#endif
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