/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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External(\_SB.PC00.XHCI.PS0X, MethodObj)
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External(\_SB.PC00.XHCI.PS3X, MethodObj)
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External(\_SB.PC00.XHCI.RHUB.PS0X, MethodObj)
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External(\_SB.PC00.XHCI.RHUB.PS2X, MethodObj)
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External(\_SB.PC00.XHCI.RHUB.PS3X, MethodObj)
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External(\_SB.PC00.XHCI.RHUB.INIR, MethodObj)
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Scope(\_SB_.PC00.XHCI) {
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OperationRegion(XPRT,PCI_Config,0x00,0x100)
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Field(XPRT,AnyAcc,NoLock,Preserve)
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{
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DVID, 16,
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Offset(0x74),
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D0D3, 2, // 0x74 BIT[1:0]
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, 6,
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PMEE, 1, // PME Enable
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, 6,
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PMES, 1, // PME Status
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Offset(0xA8), // SSCFG Reg for WPTLP
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, 13,
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MW13, 1, // 0xA8 BIT[13]
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MW14, 1, // 0xA8 BIT[14]
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, 17,
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Offset(0xB0), // SSCFG Reg for LPTLP
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, 13,
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MB13, 1, // 0xB0 BIT[13]
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MB14, 1, // 0xB0 BIT[14]
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, 17,
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Offset(0xD0),
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PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
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PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
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PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
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PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
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}
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//
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// Variable to store the maximum D state supported in S0.
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//
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Name (XFLT, 0)
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//
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// XHCI controller won't go into D3Hot during S0 until _DSM method is evaluated by filter driver.
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//
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Method(_DSM,4,serialized){
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If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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//
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// Check GUID ac340cb7-e901-45bf-b7e6-2b34ec931e23
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//
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If(LEqual(Arg0, Buffer(0x10) { 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23 }))
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{
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//
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// Only Supported value is "0x3"
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//
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If(LEqual(Arg1, 0x3))
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{
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Store(Arg1,XFLT)
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}
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}
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return(0)
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}
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Method(_S3D, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S4D, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S3W, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S4W, 0, NotSerialized)
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{
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Return(3)
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}
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//
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// Once the filter driver is installed, D3 is allowed.
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//
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Method(_S0W, 0x0, NotSerialized)
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{
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If(LEqual(XFLT, Zero))
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{
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Return(0x0)
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}
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Else
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{
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Return(0x3)
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}
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}
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Method(_PRW, 0)
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{
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Return(GPRW(0x6D, 4)) // can wakeup from S4 state
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}
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Method(_DSW, 3)
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{
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Store(Arg0, PMEE)
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}
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Method(_INI) {
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// _INI for RTD3 run conditionally if implemented in platform specific code
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If(CondRefOf(\_SB.PC00.XHCI.RHUB.INIR)) { // _INI for RTD3
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\_SB.PC00.XHCI.RHUB.INIR()
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}
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}
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//
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// GPE handler for XHCI, this is part of _Lxx handler for bus 0 PME
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//
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Method(GPEH)
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{
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If(LEqual(DVID, 0xFFFF)) {
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Return()
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}
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Store(PMES, Local0)
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Store(1, PMES) // clear PME Status
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If(LAnd(PMEE, Local0)) {
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Notify(XHCI, 0x02)
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}
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}
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OperationRegion(XHCP, SystemMemory, Add(\_SB.PC00.GPCB(), 0xA0000), 0x100)
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Field(XHCP,AnyAcc,Lock,Preserve)
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{
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Offset(0x4),
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PDBM, 16,
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Offset(0x10),
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MEMB, 64
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}
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//
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// USRA (USbR port Address), method for calculating address of first USBR port in XHCI controller
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//
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Method(USRA,0,Serialized) {
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If(LEqual(PCHV, SPTH)) { // SPT-H
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Return (15)
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} Else { // SPT-LP
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Return (11)
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}
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}
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//
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// SSPA (SuperSpeed Port Address), method for calculating address of first SS port in XHCI controller
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//
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Method(SSPA,0,Serialized) {
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If(LEqual(PCHV, SPTH)) { // SPT-H
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Return (17)
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} Else { // SPT-LP
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Return (13)
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}
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}
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Name(XRST, Zero)
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Method(_PS0,0,Serialized)
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{
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If(LEqual(^DVID,0xFFFF))
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{
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Return()
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}
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Store(^MEMB,Local2) // Save MBAR
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Store(^PDBM,Local1) // Save CMD
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And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
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//
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// Switch to D0
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//
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Store(0,^D0D3)
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Store(\XWMB,^MEMB) // Set MBAR
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Or(Local1,0x0002,^PDBM) // Set MSE
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//
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//
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//
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And(^PDBM,Not(0x02),^PDBM) // Clear MSE
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Store(Local2,^MEMB) // Restore MBAR
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Store(Local1,^PDBM) // Restore CMD
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//
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// Call platform XHC PS0 method if present
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//
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If(CondRefOf(\_SB.PC00.XHCI.PS0X))
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{
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\_SB.PC00.XHCI.PS0X()
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}
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//
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//
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If(LAnd(UWAB,LEqual(D0D3,0))) {
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//
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// If the USB WA Bit is set and any XHCI or XDCI controller is in D0
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//
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//
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// USB2 PHPY Power Gating - SW WA
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//
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// 1. BIOS writes a new command to the MTPMC register to cause the PMC to disable power gating
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Store(1,MPMC)
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// 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
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// In parallel and in response to the previous command from BIOS, PMC FW will:
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// * Make the USB2 force common lane PG match the BIOS policy (common lane PG disallowed)
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// * Disable SUS power gating in XHCI
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// * Wait for USB2 PHY side_pok to be 1
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// * Disable core power gating in USB2 PHY
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// * Disable common lane power gating in USB2 PHY (probably not necessary, consider removal)
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// * Wait for USB2 SUS restoration status to be set, and do USB2 SUS power gating restoration
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// * Get the PHY in the correct state before allowing transition to D0.
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// * Clear MSG_FULL_STS
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// BIOS sees MSG_FULL_STS clear and exits the method
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//
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While(PMFS) {
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Sleep(10)
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}
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} // End If(UWAB)
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}
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Method(_PS3,0,Serialized)
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{
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If(LEqual(^DVID,0xFFFF))
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{
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Return()
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}
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Store(^MEMB,Local2) // Save MBAR
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Store(^PDBM,Local1) // Save CMD
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And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
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//
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// Switch back to D0
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//
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Store(0,^D0D3)
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Store(\XWMB,^MEMB) // Set MBAR
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Or(Local1,0x0002,^PDBM) // Set MSE
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//
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//
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//
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And(^PDBM,Not(0x02),^PDBM) // Clear MSE
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//
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// Switch back to D3
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//
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Store(3,^D0D3)
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Store(Local2,^MEMB) // Restore MBAR
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Store(Local1,^PDBM) // Restore CMD
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//
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// Call platform XHC PS3 method if present
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//
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If(CondRefOf(\_SB.PC00.XHCI.PS3X))
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{
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\_SB.PC00.XHCI.PS3X()
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}
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If(LAnd(UWAB,LEqual(D0D3,3))) {
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//
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// If the USB WA Bit is set and XHCI is in D3
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//
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// 1. BIOS writes a new command to the MTPMC register to enable power gating
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Store(3,MPMC)
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// 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
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// In parallel and in response to the previous command from BIOS, PMC FW will:
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// * Make the USB2 force common lane PG match the BIOS policy (common lane PG allowed)
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// * Enable SUS power gating in XHCI
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// * Enable core power gating in USB2 PHY
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// * Enable common lane power gating in the USB2 PHY
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// * Clear MSG_FULL_STS
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// BIOS sees MSG_FULL_STS clear and exits the method
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//
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While(PMFS) {
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Sleep(10)
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}
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} // End If(UWAB)
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}
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// Apply S3 workaround.
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// Arguments :
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// None
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// Changes 8090 Bit 10 before S3.
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//
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Method(XHCS,0, Serialized) {
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Store(^MEMB,Local2) // Save MBAR
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Store(^PDBM,Local1) // Save CMD
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And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
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Store(\XWMB,^MEMB) // Set MBAR
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Or(Local1,0x0002,^PDBM) // Set MSE
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OperationRegion(MC11,SystemMemory,\XWMB,0x9000)
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Field(MC11,DWordAcc,Lock,Preserve)
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{
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Offset(0x8090), // HC Transfer Manager - TRM
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, 10,
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UCLI, 1, // CLEAR IN EP
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}
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Store(0x1,UCLI)
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And(^PDBM,Not(0x02),^PDBM) // Clear MSE
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Store(Local2,^MEMB) // Restore MBAR
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Store(Local1,^PDBM) // Restore CMD
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}
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//
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//
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// Check for XHCI switch UUID
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//
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// Arguments:
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// Arg0 (Buffer) : UUID
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//
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// Returns:
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// 1: It's valid UUID
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// 0: Invalid UUID
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//
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Method(CUID,1,Serialized) {
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If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) {
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Return(1)
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}
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Return(0)
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}
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Device(RHUB)
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{
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Name(_ADR, Zero)
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// PS0 Method for xHCI Root Hub
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Method(_PS0,0,Serialized)
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{
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If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC.RHUB PS0 method if present.
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//
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If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS0X))
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{
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\_SB.PC00.XHCI.RHUB.PS0X()
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}
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}
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// PS2 Method for xHCI Root Hub
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Method(_PS2,0,Serialized)
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{
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If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC.RHUB PS2 method if present.
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//
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If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS2X))
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{
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\_SB.PC00.XHCI.RHUB.PS2X()
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}
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}
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// PS3 Method for xHCI Root Hub
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Method(_PS3,0,Serialized)
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{
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If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC.RHUB PS3 method if present.
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//
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If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS3X))
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{
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\_SB.PC00.XHCI.RHUB.PS3X()
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}
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}
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//
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// High Speed Ports (without USBR)
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//
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Device(HS01)
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{
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Name(_ADR, 0x01)
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}
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Device(HS02)
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{
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Name(_ADR, 0x02)
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}
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Device(HS03)
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{
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Name(_ADR, 0x03)
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}
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Device(HS04)
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{
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Name(_ADR, 0x04)
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}
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Device(HS05)
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{
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Name(_ADR, 0x05)
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}
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Device(HS06)
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{
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Name(_ADR, 0x06)
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}
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Device(HS07)
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{
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Name(_ADR, 0x07)
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}
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Device(HS08)
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{
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Name(_ADR, 0x08)
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}
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Device(HS09)
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{
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Name(_ADR, 0x09)
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}
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Device(HS10)
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{
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Name(_ADR, 0x0A)
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}
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//
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// USBR port will be known as USBR instead of HS09 / HS15
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//
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Device(USR1)
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{
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Method(_ADR) { Return (Add(USRA(),0)) }
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}
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//
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// USBR port 2 will be known as USBR instead of xxxx
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//
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Device(USR2)
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{
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Method(_ADR) { Return (Add(USRA(),1)) }
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}
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//
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// Super Speed Ports
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//
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Device(SS01)
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{
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Method(_ADR) { Return (Add(SSPA(),0)) }
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}
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Device(SS02)
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{
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Method(_ADR) { Return (Add(SSPA(),1)) }
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}
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Device(SS03)
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{
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Method(_ADR) { Return (Add(SSPA(),2)) }
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}
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Device(SS04)
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{
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Method(_ADR) { Return (Add(SSPA(),3)) }
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}
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Device(SS05)
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{
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Method(_ADR) { Return (Add(SSPA(),4)) }
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}
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Device(SS06)
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{
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Method(_ADR) { Return (Add(SSPA(),5)) }
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}
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} // device rhub
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} //scope
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//
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// SPT-H
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//
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Scope(\_SB_.PC00.XHCI.RHUB) {
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Device(HS11)
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{
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Name(_ADR, 0xB)
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}
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Device(HS12)
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{
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Name(_ADR, 0xC)
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}
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Device(HS13)
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{
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Name(_ADR, 0xD)
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}
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Device(HS14)
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{
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Name(_ADR, 0xE)
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}
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Device(SS07)
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{
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Method(_ADR) { Return (Add(SSPA(),6)) }
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}
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Device(SS08)
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{
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Method(_ADR) { Return (Add(SSPA(),7)) }
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}
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Device(SS09)
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{
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Method(_ADR) { Return (Add(SSPA(),8)) }
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}
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Device(SS10)
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{
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Method(_ADR) { Return (Add(SSPA(),9)) }
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}
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} //scope
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