/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "UsraAccessLib.h"
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#define MAX_IO_PORT_ADDRESS 0xFFFF
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//
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// Lookup table for increment values based on transfer widths
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//
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UINT8 mInStride[] = {
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1, // UsraWidth8
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2, // UsraWidth16
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4, // UsraWidth32
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8, // UsraWidth64
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0, // UsraWidthFifo8
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0, // UsraWidthFifo16
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0, // UsraWidthFifo32
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0, // UsraWidthFifo64
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1, // UsraWidthFill8
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2, // UsraWidthFill16
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4, // UsraWidthFill32
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8 // UsraWidthFill64
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};
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//
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// Lookup table for increment values based on transfer widths
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//
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UINT8 mOutStride[] = {
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1, // UsraWidth8
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2, // UsraWidth16
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4, // UsraWidth32
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8, // UsraWidth64
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1, // UsraWidthFifo8
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2, // UsraWidthFifo16
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4, // UsraWidthFifo32
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8, // UsraWidthFifo64
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0, // UsraWidthFill8
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0, // UsraWidthFill16
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0, // UsraWidthFill32
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0 // UsraWidthFill64
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};
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/**
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This API gets the Pcie address from the given USRA Address.
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@param[in] Global Global pointer
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@param[in] Virtual Virtual address
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@param[in] Address A pointer of the address of the USRA Address Structure
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@param[out] AlignedAddress A pointer of aligned address converted from USRA address
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@retval NONE
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**/
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VOID
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GetPcieAccessAddress (
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IN VOID *Global,
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IN BOOLEAN Virtual,
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IN USRA_ADDRESS *Address,
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OUT UINTN *AlignedAddress
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)
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{
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INTN MmCfgBase;
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MmCfgBase = GetPcieSegMmcfgBaseAddress(Address);
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// TODO: add Error Check for NULL later
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*AlignedAddress = MmCfgBase + (UINTN)(Address->Attribute.RawData32[0] & 0x0fffffff);
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}
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/**
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This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register read operations.
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It transfers data from a register into a naturally aligned data buffer.
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@param[in] Address A pointer of the address of the USRA Address Structure to be read out
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@param[in] Buffer A pointer of buffer for the value read from the register
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@retval RETURN_SUCCESS The function completed successfully.
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**/
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RETURN_STATUS
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PcieRegisterRead (
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IN USRA_ADDRESS *Address,
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IN VOID *Buffer
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)
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{
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UINTN AlignedAddress;
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GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress);
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UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer);
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return RETURN_SUCCESS;
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}
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/**
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Check parameters to PcieBlkRegisterRead() function request.
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The I/O operations are carried out exactly as requested. The caller is responsible
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for satisfying any alignment and I/O width restrictions that a PI System on a
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platform might require. For example on some platforms, width requests of
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UsraWidth64 do not work. Misaligned buffers, on the other hand, will
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be handled by the driver.
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@param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
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@param[in] Width Signifies the width of the I/O or Memory operation.
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@param[in] Address The base address of the I/O operation.
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@param[in] Count The number of I/O operations to perform. The number of
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bytes moved is Width size * Count, starting at Address.
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@param[in] Buffer For read operations, the destination buffer to store the results.
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For write operations, the source buffer from which to write data.
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@retval EFI_SUCCESS The parameters for this request pass the checks.
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@retval EFI_INVALID_PARAMETER Buffer is NULL.
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@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
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@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
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@retval EFI_UNSUPPORTED The address range specified by Address, Width,
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and Count is not valid for this PI system.
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**/
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STATIC
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RETURN_STATUS
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CpuIoCheckParameter (
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IN BOOLEAN MmioOperation,
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IN USRA_ACCESS_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN VOID *Buffer
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)
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{
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UINT64 MaxCount;
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UINT64 Limit;
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//
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// Check to see if Buffer is NULL
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//
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if (Buffer == NULL) {
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Check to see if Width is in the valid range
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//
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if ((UINT32)Width >= UsraWidthMaximum) {
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return RETURN_INVALID_PARAMETER;
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}
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//
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// For FIFO type, the target address won't increase during the access,
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// so treat Count as 1
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//
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if (Width >= UsraWidthFifo8 && Width <= UsraWidthFifo64) {
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Count = 1;
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}
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//
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// Check to see if Width is in the valid range for I/O Port operations
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//
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Width = (USRA_ACCESS_WIDTH) (Width & 0x03);
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if (!MmioOperation && (Width == UsraWidth64)) {
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return RETURN_INVALID_PARAMETER;
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}
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//
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// Check to see if Address is aligned
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//
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if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
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return RETURN_UNSUPPORTED;
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}
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//
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// Check to see if any address associated with this transfer exceeds the maximum
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// allowed address. The maximum address implied by the parameters passed in is
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// Address + Size * Count. If the following condition is met, then the transfer
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// is not supported.
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//
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// Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
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//
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// Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
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// can also be the maximum integer value supported by the CPU, this range
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// check must be adjusted to avoid all oveflow conditions.
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//
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// The following form of the range check is equivalent but assumes that
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// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
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//
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Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
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if (Count == 0) {
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if (Address > Limit) {
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return RETURN_UNSUPPORTED;
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}
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} else {
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MaxCount = RShiftU64 (Limit, Width);
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if (MaxCount < (Count - 1)) {
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return RETURN_UNSUPPORTED;
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}
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if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
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return RETURN_UNSUPPORTED;
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}
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}
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//
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// Check to see if Buffer is aligned
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// (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.)
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//
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if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
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return RETURN_UNSUPPORTED;
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}
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return RETURN_SUCCESS;
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}
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/**
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This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register read operations.
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It transfers data from a register into a naturally aligned data buffer.
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@param[in] Address A pointer of the address of the USRA Address Structure to be read out
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@param[in] Buffer A pointer of buffer for the value read from the register
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@retval RETURN_SUCCESS The function completed successfully.
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@retval Others Some error occurs when executing CpuIoCheckParameter function.
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**/
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RETURN_STATUS
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PcieBlkRegisterRead (
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IN USRA_ADDRESS *Address,
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IN VOID *Buffer
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)
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{
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UINT8 InStride;
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UINT8 OutStride;
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RETURN_STATUS Status;
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UINTN AlignedAddress;
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UINT32 ReadCount = Address->PcieBlk.Count;
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UINT8 *UINT8Buffer;
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GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress);
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Status = CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, AlignedAddress, ReadCount, Buffer);
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if (RETURN_ERROR (Status)) {
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return Status;
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}
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InStride = mInStride[Address->Attribute.AccessWidth];
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OutStride = mOutStride[Address->Attribute.AccessWidth];
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for (UINT8Buffer = Buffer; ReadCount > 0; AlignedAddress += InStride, UINT8Buffer += OutStride, ReadCount--) {
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UsraRegAlignedRead((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth & 0x03), AlignedAddress, (VOID *)UINT8Buffer);
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}
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return RETURN_SUCCESS;
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}
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/**
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This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register write operations.
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It transfers data from a naturally aligned data buffer into a register.
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@param[in] Address A pointer of the address of the USRA Address Structure to be written
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@param[in] Buffer A pointer of buffer for the value write to the register
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@retval RETURN_SUCCESS The function completed successfully.
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**/
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RETURN_STATUS
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PcieRegisterWrite (
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IN USRA_ADDRESS *Address,
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OUT VOID *Buffer
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)
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{
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UINTN AlignedAddress;
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GetPcieAccessAddress(NULL, 0, Address, &AlignedAddress);
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UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer);
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if (FeaturePcdGet (PcdUsraSupportS3))
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{
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if(Address->Attribute.S3Enable)
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{
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S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribute.AccessWidth, (UINT64)AlignedAddress, 1, Buffer);
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}
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}
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return RETURN_SUCCESS;
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}
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/**
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This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register write operations.
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It transfers data from a naturally aligned data buffer into a register.
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@param[in] Address A pointer of the address of the USRA Address Structure to be written
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@param[in] Buffer A pointer of buffer for the value write to the register
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@retval RETURN_SUCCESS The function completed successfully.
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@retval Others Some error occurs when executing CpuIoCheckParameter function.
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**/
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RETURN_STATUS
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PcieBlkRegisterWrite (
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IN USRA_ADDRESS *Address,
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OUT VOID *Buffer
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)
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{
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UINT8 InStride;
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UINT8 OutStride;
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RETURN_STATUS Status;
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UINTN AlignedAddress;
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UINT32 WriteCount = Address->PcieBlk.Count;
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UINT8 *UINT8Buffer;
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GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress);
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Status = CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, AlignedAddress, WriteCount, Buffer);
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if (RETURN_ERROR (Status)) {
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return Status;
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}
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InStride = mInStride[Address->Attribute.AccessWidth];
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OutStride = mOutStride[Address->Attribute.AccessWidth];
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for (UINT8Buffer = Buffer; WriteCount > 0; AlignedAddress += InStride, UINT8Buffer += OutStride, WriteCount--) {
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UsraRegAlignedWrite((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth & 0x03), AlignedAddress, (VOID *)UINT8Buffer);
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if (FeaturePcdGet (PcdUsraSupportS3)) {
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if(Address->Attribute.S3Enable) {
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S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)(Address->Attribute.AccessWidth & 0x03), (UINT64)AlignedAddress, 1, (VOID *)UINT8Buffer);
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}
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}
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}
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return RETURN_SUCCESS;
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}
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/**
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This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a
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register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register
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@param[in] Address A pointer of the address of the silicon register to be modified
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@param[in] AndBuffer A pointer of buffer for the value used for AND operation
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A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr()
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@param[in] OrBuffer A pointer of buffer for the value used for OR operation
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A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd()
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@retval RETURN_SUCCESS The function completed successfully.
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**/
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RETURN_STATUS
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PcieRegisterModify (
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IN USRA_ADDRESS *Address,
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IN VOID *AndBuffer,
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IN VOID *OrBuffer
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)
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{
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UINT64 Data;
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UINT8 WidthTable[] = {1,2,4,8};
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PcieRegisterRead(Address, &Data);
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DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attribute.AccessWidth]);
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PcieRegisterWrite(Address, &Data);
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return RETURN_SUCCESS;
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}
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