/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <SysHost.h>
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#include "CpuPciAccess.h"
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
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#include <Library/DebugLib.h>
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#endif
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#ifndef IA32
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#include "Library/IoLib.h"
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#include <Protocol/IioUds.h>
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#include <Library/UefiBootServicesTableLib.h>
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static EFI_IIO_UDS_PROTOCOL *mIioUds;
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IIO_UDS *mIioUdsDataPtr;
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CPU_CSR_ACCESS_VAR *PCpuCsrAccessVarGlobal = NULL;
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#endif
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#ifndef IA32
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CPU_CSR_ACCESS_VAR CpuCsrAccessVarGlobal;
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#endif
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//
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// Disable warning for unsued input parameters
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//
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#ifdef _MSC_VER
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#pragma warning(disable : 4100)
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#pragma warning(disable : 4013)
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#pragma warning(disable : 4306)
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#endif
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//
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// PCI function translation table; note that this table doesn't capture the function
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// information for all instances of a box. It only captures for the first instance.
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// It has to be translated for other instances after the look up is done.
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//
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STATIC UINT8 FunTbl[MAX_CPU_TYPES][MAX_BOX_TYPES][8] = {
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{
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{0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA MISC 0
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{0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA PMA 1
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{0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA CMS 2
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{0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // CHABC 3
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{0, 1, 2, 3, 4, 5, 6, 7 }, // PCU 4
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{0, 1, 2, 3, 4, 5, 6, 7 }, // VCU 5
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{0, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2MEM 6
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{0, 4, 0, 0, 4, 0, 0xFF, 0xFF}, // MC 7 //SKX:Should be {0, 1, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
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{0, 2, 4, 0, 2, 4, 0xFF, 0xFF}, // MCIO DDRIO 8 //SKX:should be {0, 1, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF}
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{0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // KTI 9
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{0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // M3KTI 10
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{2, 6, 2, 2, 6, 2, 0xFF, 0xFF}, // MCDDC 11 //SKX:SHould be {2, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // MCDDC These entries all seem wrong but work
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{0, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2UPCIE 12
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{0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO DMI 13
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{0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIE 14
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{0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIENTB 15
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{0, 1, 2, 3, 4, 5, 6, 7 }, // IIOCB 16
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{0, 1, 2, 4, 5, 6, 0xFF, 0xFF}, // IIO VTD 17
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{0, 0, 7, 7, 4, 4, 0xFF, 0xFF}, // IIO_RTO 18
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{0, 1, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // UBOX 19
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}, // SKX
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};
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STATIC UINT8 m2pcieDevTable[MAX_SKX_M2PCIE] = { 22, 21, 22, 23, 21};
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/**
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Populate CpuCsrAccessVar structure.
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@param host - pointer to the system host root structure
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@param CpuCsrAccessVar - pointer to CpuCsrAccessVar structure to be populated
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@retval None
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**/
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VOID
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GetCpuCsrAccessVar_RC (
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PSYSHOST host,
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CPU_CSR_ACCESS_VAR *CpuCsrAccessVar
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)
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{
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#ifndef IA32
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EFI_STATUS Status;
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#endif
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if (host != NULL) {
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CpuDeadLoop ();
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}
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#ifndef IA32
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if (host == NULL) {
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if(PCpuCsrAccessVarGlobal == NULL){ //check if 1st time, if yes, then need to update
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// Locate the IIO Protocol Interface
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Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid, NULL, &mIioUds);
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mIioUdsDataPtr = (IIO_UDS *)mIioUds->IioUdsPtr;
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//ASSERT_EFI_ERROR (Status);
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PCpuCsrAccessVarGlobal = &CpuCsrAccessVarGlobal;
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for (socket = 0; socket < MAX_SOCKET; socket++) {
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CpuCsrAccessVarGlobal.stackPresentBitmap[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].stackPresentBitmap;
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CpuCsrAccessVarGlobal.SocketFirstBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketFirstBus;
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CpuCsrAccessVarGlobal.SocketLastBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketLastBus;
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CpuCsrAccessVarGlobal.segmentSocket[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].segmentSocket;
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for (ctr = 0; ctr < MAX_IIO_STACK; ctr++) {
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CpuCsrAccessVarGlobal.StackBus[socket][ctr] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].StackBus[ctr];
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}
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}
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CpuCsrAccessVarGlobal.cpuType = mIioUdsDataPtr->SystemStatus.cpuType;
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CpuCsrAccessVarGlobal.stepping = mIioUdsDataPtr->SystemStatus.MinimumCpuStepping;
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CpuCsrAccessVarGlobal.socketPresentBitMap = mIioUdsDataPtr->SystemStatus.socketPresentBitMap;
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CpuCsrAccessVarGlobal.FpgaPresentBitMap = mIioUdsDataPtr->SystemStatus.FpgaPresentBitMap;
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CpuCsrAccessVarGlobal.mmCfgBase = (UINT32)mIioUdsDataPtr->PlatformData.PciExpressBase;
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CpuCsrAccessVarGlobal.numChPerMC = mIioUdsDataPtr->SystemStatus.numChPerMC;
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CpuCsrAccessVarGlobal.maxCh = mIioUdsDataPtr->SystemStatus.maxCh;
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CpuCsrAccessVarGlobal.maxIMC = mIioUdsDataPtr->SystemStatus.maxIMC;
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}
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if ((PCpuCsrAccessVarGlobal != NULL) && (CpuCsrAccessVarGlobal.socketPresentBitMap != mIioUdsDataPtr->SystemStatus.socketPresentBitMap)) {
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for (socket = 0; socket < MAX_SOCKET; socket++) {
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CpuCsrAccessVarGlobal.stackPresentBitmap[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].stackPresentBitmap;
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CpuCsrAccessVarGlobal.SocketFirstBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketFirstBus;
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CpuCsrAccessVarGlobal.SocketLastBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketLastBus;
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CpuCsrAccessVarGlobal.segmentSocket[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].segmentSocket;
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for (ctr = 0; ctr < MAX_IIO_STACK; ctr++) {
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CpuCsrAccessVarGlobal.StackBus[socket][ctr] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].StackBus[ctr];
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}
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}
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CpuCsrAccessVarGlobal.cpuType = mIioUdsDataPtr->SystemStatus.cpuType;
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CpuCsrAccessVarGlobal.stepping = mIioUdsDataPtr->SystemStatus.MinimumCpuStepping;
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CpuCsrAccessVarGlobal.socketPresentBitMap = mIioUdsDataPtr->SystemStatus.socketPresentBitMap;
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CpuCsrAccessVarGlobal.FpgaPresentBitMap = mIioUdsDataPtr->SystemStatus.FpgaPresentBitMap;
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CpuCsrAccessVarGlobal.mmCfgBase = (UINT32)mIioUdsDataPtr->PlatformData.PciExpressBase;
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CpuCsrAccessVarGlobal.numChPerMC = mIioUdsDataPtr->SystemStatus.numChPerMC;
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CpuCsrAccessVarGlobal.maxCh = mIioUdsDataPtr->SystemStatus.maxCh;
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CpuCsrAccessVarGlobal.maxIMC = mIioUdsDataPtr->SystemStatus.maxIMC;
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}
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for (socket = 0; socket < MAX_SOCKET; socket++) {
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CpuCsrAccessVar->stackPresentBitmap[socket] = CpuCsrAccessVarGlobal.stackPresentBitmap[socket];
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CopyMem (&CpuCsrAccessVar->StackBus[socket], &CpuCsrAccessVarGlobal.StackBus[socket], MAX_IIO_STACK);
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}
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CpuCsrAccessVar->cpuType = CpuCsrAccessVarGlobal.cpuType;
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//CpuCsrAccessVar->stepping = CpuCsrAccessVarGlobal.stepping;
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CpuCsrAccessVar->socketPresentBitMap = CpuCsrAccessVarGlobal.socketPresentBitMap;
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CpuCsrAccessVar->FpgaPresentBitMap = CpuCsrAccessVarGlobal.FpgaPresentBitMap;
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//CpuCsrAccessVar->mmCfgBase = CpuCsrAccessVarGlobal.mmCfgBase;
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CpuCsrAccessVar->numChPerMC = CpuCsrAccessVarGlobal.numChPerMC;
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CpuCsrAccessVar->maxCh = CpuCsrAccessVarGlobal.maxCh;
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//CpuCsrAccessVar->maxIMC = CpuCsrAccessVarGlobal.maxIMC;
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}
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#endif
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}
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/**
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Stall execution after internal assertion fails
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@param haltOnError - 1 stalls in infinite loop; 0 returns to caller
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@retval None
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**/
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VOID RcDeadLoop (
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UINT8 haltOnError
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)
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{
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//
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// Prevent from optimizing out
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//
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while (*(volatile UINT8 *) &haltOnError);
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}
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/**
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CsrAccess specific print to serial output
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@param host - Pointer to the system host (root) structure
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@param Format - string format
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@retval N/A
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**/
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VOID
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CpuCsrAccessError (
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PSYSHOST host,
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char* Format,
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...
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)
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{
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UINT8 haltOnError;
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#ifdef SERIAL_DBG_MSG
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
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UINT32 *pData32;
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#endif
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va_list Marker;
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va_start (Marker, Format);
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
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if (host != NULL) {
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pData32 = (UINT32 *)Marker;
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if( (*pData32 & 0xFFFFFF00) == 0xFFFFFF00){ // check if input is one byte only
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*pData32 = *pData32 & 0x000000FF;
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} if( (*pData32 & 0xFFFF0000) == 0xFFFF0000){ // check if input is word only
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*pData32 = *pData32 & 0x0000FFFF;
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}
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DEBUG ((
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DEBUG_ERROR, Format, *pData32
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));
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}
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#else
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if (host != NULL) {
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rcVprintf (host, Format, Marker);
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}
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#endif
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va_end (Marker);
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#endif
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haltOnError = 1;
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RcDeadLoop (haltOnError);
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return;
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}
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/**
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Returns the CPU Index for MC func tbl lookup based on CPU type and CPU sub type.
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This index will be used for MC box instance -> function mapping look-up
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@param host - Pointer to the system host (root) structure
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@retval Index for CPU type
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**/
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STATIC
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UINT8
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GetCpuIndex (
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PSYSHOST host
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)
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{
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UINT8 cpuIndex = 0xFF;
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cpuIndex = 0;
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return cpuIndex;
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}
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/**
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Indetifies the bus number for given SocId & BoxType
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@param host - Pointer to the system host (root) structure
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@param SocId - CPU Socket Node number (Socket ID)
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@param BoxType - Box Type; values come from CpuPciAccess.h
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@retval PCI bus number
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**/
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UINT32
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GetBusNumber (
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PSYSHOST host,
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UINT8 SocId,
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UINT8 BoxType,
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UINT8 BoxInst,
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UINT8 FuncBlk,
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CPU_CSR_ACCESS_VAR *CpuCsrAccessVar
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)
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{
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UINT32 Bus = 0;
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UINT8 TempStack = 0;
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// Make sure SocId or Fpga is valid
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if ((!((CpuCsrAccessVar->socketPresentBitMap & (1 << SocId)) && (BoxType != BOX_FPGA)))) {
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if ((!((CpuCsrAccessVar->FpgaPresentBitMap & (1 << SocId)) && (BoxType == BOX_FPGA)))) {
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CpuCsrAccessError (host, "\nInvalid Socket Id %d. \n", SocId);
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}
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}
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//
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// Each socket is assigned multiple buses
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// Check the box type and return the appropriate bus number.
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//
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if ((BoxType == BOX_MC) ||
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(BoxType == BOX_MCDDC) ||
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(BoxType == BOX_MCIO) ||
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(BoxType == BOX_M2MEM)) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK1];
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} else if (BoxType == BOX_UBOX) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK];
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} else if ((BoxType == BOX_IIO_PCIE_DMI) ||
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(BoxType == BOX_IIO_CB)) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK];
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} else if (BoxType == BOX_IIO_PCIE) {
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//
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// IIO_PCIE is used to access all pcie ports in all stacks
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//
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if (BoxInst == 0) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK];
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} else {
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TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4);
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if (TempStack < MAX_IIO_STACK) {
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Bus = CpuCsrAccessVar->StackBus[SocId][TempStack];
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} else {
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CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", BoxInst);
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}
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}
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} else if (BoxType == BOX_IIO_VTD) {
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TempStack = IIO_CSTACK + BoxInst;
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if (TempStack < MAX_IIO_STACK) {
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Bus = CpuCsrAccessVar->StackBus[SocId][TempStack];
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} else {
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CpuCsrAccessError (host, "\nInvalid BOX_IIO_VTD BoxInstance %d. \n", BoxInst);
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}
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} else if (BoxType == BOX_IIO_PCIE_NTB) {
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if (BoxInst > 0) {
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TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4);
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if (TempStack < MAX_IIO_STACK) {
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Bus = CpuCsrAccessVar->StackBus[SocId][TempStack];
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} else {
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CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d. \n", BoxInst);
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}
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} else {
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CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d. \n", BoxInst);
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}
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} else if (BoxType == BOX_IIO_RTO) {
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if (FuncBlk == IIO_RTO) {
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//
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// IIO_RTO is used to access all pcie ports in all stacks same as iio_pcie
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//
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if (BoxInst == 0) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK];
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} else {
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TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4);
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if (TempStack < MAX_IIO_STACK) {
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Bus = CpuCsrAccessVar->StackBus[SocId][TempStack];
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} else {
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CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", BoxInst);
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}
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}
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} else if ((FuncBlk == IIO_RTO_GLOBAL) || (FuncBlk == IIO_RTO_VTD)) {
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//
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// IIO_RTO_GLOBAL and IIO_RTO_VTD maps 1 instance per c/p/m stack
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//
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if ((IIO_CSTACK + BoxInst) < MAX_IIO_STACK) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK + BoxInst];
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}
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} else if ((FuncBlk == IIO_RTO_VTD_DMI) ||
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(FuncBlk == IIO_RTO_DMI) ||
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(FuncBlk == IIO_RTO_GLOBAL_DMI)) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK];
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} else {
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CpuCsrAccessError (host, "\nInvalid BoxType %d, Functional block %d. \n", BoxType, FuncBlk);
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}
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} else if ((BoxType == BOX_CHA_MISC) ||
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(BoxType == BOX_CHA_PMA) ||
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(BoxType == BOX_CHA_CMS) ||
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(BoxType == BOX_CHABC) ||
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(BoxType == BOX_PCU) ||
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(BoxType == BOX_VCU)) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK0];
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} else if ((BoxType == BOX_M2UPCIE) ||
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(BoxType == BOX_KTI) ||
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(BoxType == BOX_M3KTI)) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK2];
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} else if (BoxType == BOX_FPGA) {
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Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK];
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} else {
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// Error
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CpuCsrAccessError (host, "\nInvalid BoxType %d. \n", BoxType);
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}
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return Bus;
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}
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/**
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Indetifies the device number for given Box Type & Box Instance
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@param host - Pointer to the system host (root) structure
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@param BoxType - Box Type; values come from CpuPciAccess.h
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@param BoxInst - Box Instance, 0 based
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@param FuncBlk - Functional Block; values come from CpuPciAccess.h
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@retval PCI Device number
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**/
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UINT32
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GetDeviceNumber (
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PSYSHOST host,
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UINT8 BoxType,
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UINT8 BoxInst,
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UINT8 FuncBlk,
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CPU_CSR_ACCESS_VAR *CpuCsrAccessVar
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)
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{
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UINT32 Dev = 0;
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UINT8 CpuType, NumChPerMC;
|
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CpuType = CpuCsrAccessVar->cpuType;
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NumChPerMC = CpuCsrAccessVar->numChPerMC;
|
|
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//
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// Translate the Box Type & Instance into PCI Device number.
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//
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switch (BoxType) {
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case BOX_MC:
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case BOX_MCDDC:
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if (CpuType == CPU_SKX) {
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switch (BoxInst) {
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case 0:
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case 1:
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Dev = 10;
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break;
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case 2:
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Dev = 11;
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break;
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case 3:
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case 4:
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Dev = 12;
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break;
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case 5:
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Dev = 13;
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break;
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}
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} else {
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CpuCsrAccessError (host, "\nInvalid Cpu type.\n");
|
}
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break;
|
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case BOX_MCIO:
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if (CpuType == CPU_SKX) {
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Dev = 22 + (BoxInst / NumChPerMC);
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} else {
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CpuCsrAccessError (host, "\nInvalid Cpu type.\n");
|
}
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break;
|
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case BOX_M2MEM:
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if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_M2MEM)) {
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Dev = 8 + BoxInst;
|
} else {
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CpuCsrAccessError (host, "\nInvalid M2MEM Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_CHA_MISC:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) {
|
if (BoxInst < 8) {
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Dev = 8;
|
} else if (BoxInst < 16) {
|
Dev = 9;
|
} else if (BoxInst < 24) {
|
Dev = 10;
|
} else if (BoxInst < 28) {
|
Dev = 11;
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_CHA_PMA:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) {
|
if (BoxInst < 8) {
|
Dev = 14;
|
} else if (BoxInst < 16) {
|
Dev = 15;
|
} else if (BoxInst < 24) {
|
Dev = 16;
|
} else if (BoxInst < 28) {
|
Dev = 17;
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_CHA_CMS:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) {
|
if (BoxInst < 8) {
|
Dev = 20;
|
} else if (BoxInst < 16) {
|
Dev = 21;
|
} else if (BoxInst < 24) {
|
Dev = 22;
|
} else if (BoxInst < 28) {
|
Dev = 23;
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_CHABC:
|
if ((CpuType == CPU_SKX) && (BoxInst == 0)) {
|
Dev = 29;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid CHABC Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_PCU:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_PCU)) {
|
Dev = 30;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid PCU Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_VCU:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_VCU)) {
|
Dev = 31;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid VCU Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_KTI:
|
/*
|
Dev # KTI(phy,logic)#
|
14 0 0
|
15 1 1
|
16 2 2
|
*/
|
if (CpuType == CPU_SKX) {
|
if (BoxInst < MAX_SKX_KTIAGENT ) {
|
Dev = 14 + BoxInst;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n", BoxInst);
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid Cpu type.\n");
|
}
|
break;
|
|
case BOX_M3KTI:
|
/*
|
Logical M3KTI # Dev # Fun #
|
KTI01 0 18 0
|
KTI23 1 18 4
|
*/
|
|
if (CpuType == CPU_SKX) {
|
if (BoxInst < 2 ) {
|
Dev = 18;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid Box instance.\n");
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid Cpu type.\n");
|
}
|
break;
|
|
case BOX_M2UPCIE:
|
if (CpuType == CPU_SKX) {
|
if (BoxInst < MAX_SKX_M2PCIE) {
|
Dev = m2pcieDevTable[BoxInst];
|
} else {
|
CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n", BoxInst);
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid Cpu type.\n");
|
}
|
break;
|
|
case BOX_IIO_PCIE_DMI:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO)) {
|
Dev = 0;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO PCIE DMI Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_IIO_PCIE:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO_PCIE)) {
|
if (BoxInst == 0) {
|
// Cstack
|
Dev = 0;
|
} else {
|
// M/Pstacks
|
Dev = 0 + ((BoxInst-1) % 4);
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_IIO_PCIE_NTB:
|
if ((CpuType == CPU_SKX)) {
|
Dev = 0;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_IIO_CB:
|
if ((CpuType == CPU_SKX)) {
|
Dev = 4;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO CB Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_IIO_VTD:
|
if ((CpuType == CPU_SKX)) {
|
Dev = 5;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO VTD Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_IIO_RTO:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO_RTO)) {
|
Dev = 7;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_UBOX:
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_UBOX)) {
|
Dev = 8;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid Ubox Instance Number %d. \n", BoxInst);
|
//Note: the fatal error function writes to UBOX CSR and recurses forever (until stack is gone).
|
}
|
break;
|
case BOX_FPGA:
|
if ((CpuType == CPU_SKX) && (BoxInst == 0)) {
|
Dev = 16;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid FPGA Instance number %d. \n", BoxInst);
|
}
|
break;
|
|
default:
|
CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType);
|
}
|
|
if (Dev > 31) {
|
CpuCsrAccessError (host, "\nInvalid Device %d accessed for Box Type %d and Box Instance %d. \n", Dev, BoxType, BoxInst);
|
}
|
return Dev;
|
}
|
|
/**
|
|
Indetifies the function number for given BoxType, BoxInst & Functional Block
|
|
@param host - Pointer to the system host (root) structure
|
@param BoxType - Box Type; values come from CpuPciAccess.h
|
@param BoxInst - Box Instance, 0 based
|
@param FuncBlk - Functional Block; values come from CpuPciAccess.h
|
|
@retval PCI Function number
|
|
**/
|
UINT32
|
GetFunctionNumber (
|
PSYSHOST host,
|
UINT8 BoxType,
|
UINT8 BoxInst,
|
UINT8 FuncBlk,
|
CPU_CSR_ACCESS_VAR *CpuCsrAccessVar
|
)
|
{
|
UINT32 Fun = 0;
|
UINT8 CpuIndex, CpuType, NumChPerMC;
|
|
CpuType = CpuCsrAccessVar->cpuType;
|
NumChPerMC = CpuCsrAccessVar->numChPerMC;
|
|
// Get the CPU type, sub type
|
CpuIndex = GetCpuIndex(host);
|
|
//
|
// Translate the Box Type & Functional Block into PCI function number. Note that the box type & instance number
|
// passed to this routine are assumed to be valid; here we only need to validate if the function number is correct
|
// after the look up is done.
|
//
|
|
switch (BoxType) {
|
|
case BOX_MC:
|
|
if (FuncBlk == 0 || FuncBlk == 1) {
|
Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk;
|
} else {
|
Fun = 4;
|
}
|
break;
|
|
case BOX_MCDDC:
|
|
Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk;
|
break;
|
|
case BOX_MCIO:
|
|
if (FuncBlk == 2) {
|
Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + 3;
|
|
} else {
|
Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk;
|
}
|
break;
|
|
case BOX_CHA_MISC:
|
case BOX_CHA_PMA:
|
case BOX_CHA_CMS:
|
//
|
// For Cha, no table look up is needed; the function number can be obtained from instance number.
|
//
|
if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) {
|
Fun = (BoxInst % 8);
|
}
|
break;
|
|
case BOX_M3KTI:
|
/*
|
Logical M3KTI # Dev # Fun #
|
KTI01 0 18 0
|
KTI23 1 18 4
|
*/
|
|
Fun = FunTbl[CpuType][BoxType][FuncBlk];
|
if (BoxInst == 1) {
|
Fun = Fun + 4;
|
}
|
break;
|
|
case BOX_M2MEM:
|
case BOX_CHABC:
|
case BOX_PCU:
|
case BOX_VCU:
|
case BOX_IIO_PCIE_DMI:
|
case BOX_IIO_PCIE:
|
case BOX_IIO_PCIE_NTB:
|
case BOX_IIO_CB:
|
case BOX_IIO_VTD:
|
case BOX_UBOX:
|
Fun = FunTbl[CpuType][BoxType][FuncBlk];
|
break;
|
|
case BOX_M2UPCIE:
|
Fun = FunTbl[CpuType][BoxType][FuncBlk];
|
if (BoxInst == 2 || BoxInst == 4) { // M2PCIE2 & M2MCP1
|
Fun = Fun + 4;
|
}
|
break;
|
|
case BOX_KTI:
|
Fun = FunTbl[CpuType][BoxType][FuncBlk];
|
if (BoxInst >=9 ) {
|
Fun = Fun + 4;
|
}
|
break;
|
|
case BOX_IIO_RTO:
|
if ((BoxInst < MAX_ALL_IIO_RTO) && (FunTbl[CpuType][BoxType][FuncBlk] != 0xFF)) {
|
if (FuncBlk == IIO_RTO) {
|
if (BoxInst == 0) {
|
// Cstack
|
Fun = 0;
|
} else {
|
// M/Pstacks
|
Fun = 0 + ((BoxInst-1) % 4);
|
}
|
} else {
|
Fun = FunTbl[CpuType][BoxType][FuncBlk];
|
}
|
} else {
|
CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
case BOX_FPGA:
|
if (BoxInst == 0) {
|
Fun = 0;
|
} else {
|
CpuCsrAccessError (host, "\nInvalid FPGA Box Instance Number %d. \n", BoxInst);
|
}
|
break;
|
|
default:
|
CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType);
|
}
|
|
if (Fun > 7) {
|
CpuCsrAccessError (host, "\nInvalid Functional Block %d accessed for CPUType %d CPUIndex %d Box Type %d and Box Instance %d. \n",
|
FuncBlk, CpuType, CpuIndex, BoxType, BoxInst);
|
}
|
|
return Fun;
|
}
|
