/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _mem_platform_h
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#define _mem_platform_h
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#include "DataTypes.h"
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#ifdef SERIAL_DBG_MSG
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#define MRC_TRACE 1
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#endif
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//
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// Compatible BIOS Data Structure
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//
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#define BDAT_SUPPORT 0 //Memory Data Schema 4 and RMT Schema 5 of BDAT 4.0
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//
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// QR support
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//
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#define QR_DIMM_SUPPORT 1
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//
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// Define to enable DIMM margin checking
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//
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#define MARGIN_CHECK 1
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//
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// Define to enable SODIMM module support
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//
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#define SODIMM_SUPPORT 1
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//
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// Define to enable ME UMA support
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//
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//#define ME_SUPPORT_FLAG 1
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//
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// Define to enable XMP
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//
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#define XMP_SUPPORT 1
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// Define to enable DEBUG for NVMCTLR (LATE CMD CLK)
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//#define DEBUG_LATECMDCLK 1
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// Define to enable MRS Stacking
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//#define MRS_STACKING 1
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//
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// Define to max ppr
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//
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#define MAX_PPR_ADDR_ENTRIES 20
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//
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//-------------------------------------
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// DVP Platform-specific defines
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//-------------------------------------
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//
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#ifdef DVP_PLATFORM
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#endif // DVP_PLATFORM
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//
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//-------------------------------------
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// CRB Platform-specific defines
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//-------------------------------------
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//
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#ifdef CRB_PLATFORM
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#endif // CRB_PLATFORM
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#ifndef MAX_HA
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#define MAX_HA 2 // Number of Home Agents / IMCs
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#endif
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//SKX_TODO: I have removed NonPOR elements, I will delete this line before submit
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#endif // _mem_platform_h
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