/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _USB_DEBUG_PORT_INTERNAL_H
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#define _USB_DEBUG_PORT_INTERNAL_H
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#include "DataTypes.h"
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#define PCI_VENDOR_ID_OFFSET 0x00
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#define PCI_DEVICE_ID_OFFSET 0x02
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#define PCI_COMMAND_OFFSET 0x04
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#define PCI_PRIMARY_STATUS_OFFSET 0x06
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#define PCI_REVISION_ID_OFFSET 0x08
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#define PCI_CLASSCODE_OFFSET 0x09
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#define PCI_SUBCLASSCODE_OFFSET 0x0A
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#define PCI_BASECLASSCODE_OFFSET 0x0B // Base Class Code Register
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#define PCI_CACHELINE_SIZE_OFFSET 0x0C
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#define PCI_LATENCY_TIMER_OFFSET 0x0D
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#define PCI_HEADER_TYPE_OFFSET 0x0E
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#define PCI_BIST_OFFSET 0x0F
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#define PCI_BASE_ADDRESSREG_OFFSET 0x10
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#define PCI_CARDBUS_CIS_OFFSET 0x28
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#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
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#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
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#define PCI_SID_OFFSET 0x2E // SubSystem ID
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#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
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#define PCI_EXPANSION_ROM_BASE 0x30
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#define PCI_CAPBILITY_POINTER_OFFSET 0x34
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#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
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#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
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#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
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#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
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#define PCI_CLASS_SERIAL 0x0C
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#define PCI_CLASS_SERIAL_USB 0x03
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#define IS_BIT_SET(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) != 0)
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#define IS_BIT_CLEAR(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) == 0)
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#define SET_R32_BIT(Register, BitMask) \
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{ \
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UINT32 RegisterValue = *(volatile UINT32 *)(Register); \
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RegisterValue |= (UINT32)(BitMask); \
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*(volatile UINT32 *)(Register) = RegisterValue; \
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}
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#define CLR_R32_BIT(Register, BitMask) \
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{ \
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UINT32 RegisterValue = *(volatile UINT32 *)(Register); \
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RegisterValue &= (UINT32)(~(BitMask)); \
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*(volatile UINT32 *)(Register) = RegisterValue; \
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}
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#define CLR_AND_SET_R32_BIT(Register, BitMask, Value) \
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{ \
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UINT32 RegisterValue = *(volatile UINT32 *)(Register); \
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RegisterValue &= (UINT32)(~(BitMask)); \
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RegisterValue |= (UINT32)(Value); \
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*(volatile UINT32 *)(Register) = RegisterValue; \
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}
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#define SET_R16_BIT(Register, BitMask) \
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{ \
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UINT16 RegisterValue = *(volatile UINT16 *)(Register); \
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RegisterValue |= (UINT16)(BitMask); \
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*(volatile UINT16 *)(Register) = RegisterValue; \
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}
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#define CLR_R16_BIT(Register, BitMask) \
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{ \
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UINT16 RegisterValue = *(volatile UINT16 *)(Register); \
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RegisterValue &= (UINT16)(~(BitMask)); \
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*(volatile UINT16 *)(Register) = RegisterValue; \
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}
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#define SET_R8_BIT(Register, BitMask) \
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{ \
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UINT8 RegisterValue = *(volatile UINT8 *)(Register); \
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RegisterValue |= (UINT8)(BitMask); \
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*(volatile UINT8 *)(Register) = RegisterValue; \
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}
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#define CLR_R8_BIT(Register, BitMask) \
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{ \
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UINT8 RegisterValue = *(volatile UINT8 *)(Register); \
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RegisterValue &= (UINT8)(~(BitMask)); \
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*(volatile UINT8 *)(Register) = RegisterValue; \
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}
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#define PCI_CLASS_SERIAL_USB_EHCI 0x20
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#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
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#define PCI_USB2_SBRN_OFFSET 0x60
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#define PCI_PRIMARY_BUS_NUMBER_OFFSET 0x18
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#define PCI_SECONDARY_BUS_NUMBER_OFFSET 0x19
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#define PCI_SUBORDINATE_BUS_NUMBER_OFFSET 0x1A
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#define PCI_BRIDGE_MBASE_OFFSET 0x20
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#define PCI_BRIDGE_MLIMIT_OFFSET 0x22
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#define PCI_EHCI_DEFAULT_BUS_NUMBER 0x00
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#define PCI_EHCI_DEFAULT_DEVICE_NUMBER 0x1D
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#define PCI_EHCI_DEFAULT_FUNCTION_NUMBER 0x00
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#define PCI_EHCI_DEFAULT_DEBUG_CAPID_OFFSET 0x58
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#define PCI_EHCI_DEFAULT_DEBUG_BASE_OFFSET 0x5A
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//
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// USB PIDs
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//
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#define USB2_PID_TOKEN_OUT 0xE1
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#define USB2_PID_TOKEN_IN 0x69
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#define USB2_PID_TOKEN_SOF 0xA5
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#define USB2_PID_TOKEN_SETUP 0x2D
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#define USB2_PID_DATA0 0xC3
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#define USB2_PID_DATA1 0x4B
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#define USB2_PID_DATA2 0x87
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#define USB2_PID_MDATA 0x0F
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#define USB2_PID_HANDSHAKE_ACK 0xD2
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#define USB2_PID_HANDSHAKE_NAK 0x5A
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#define USB2_PID_HANDSHAKE_STALL 0x1E
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#define USB2_PID_HANDSHAKE_NYET 0x96
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#define USB2_PID_SPECIAL_PRE 0x3C
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#define USB2_PID_SPECIAL_ERR 0x3C
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#define USB2_PID_SPECIAL_SPLIT 0x78
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#define USB2_PID_SPECIAL_PING 0xB4
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#define USB2_PID_SPECIAL_RESERVED 0xF0
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//
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// USB2 Debug Port Register
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//
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#define USB2_DEBUG_PORT_STATUS_OWNER 0x40000000
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#define USB2_DEBUG_PORT_STATUS_ENABLED 0x10000000
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#define USB2_DEBUG_PORT_STATUS_DONE 0x00010000
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#define USB2_DEBUG_PORT_STATUS_INUSE 0x00000400
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#define USB2_DEBUG_PORT_STATUS_EXCEPTION 0x00000380
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#define USB2_DEBUG_PORT_STATUS_ERROR 0x00000040
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#define USB2_DEBUG_PORT_STATUS_GO 0x00000020
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#define USB2_DEBUG_PORT_STATUS_WRITE 0x00000010
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#define USB2_DEBUG_PORT_STATUS_LENGTH 0x0000000F
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#define USB2_DEBUG_PORT_DEFAULT_ADDRESS 127
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#define USB2_DEBUG_PORT_DEVICE_BUFFER_MAX 8
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typedef struct _USB2_DEBUG_PORT_REGISTER {
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UINT32 ControlStatus;
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UINT8 TokenPid;
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UINT8 SendPid;
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UINT8 ReceivedPid;
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UINT8 Reserved1;
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UINT8 DataBuffer[USB2_DEBUG_PORT_DEVICE_BUFFER_MAX];
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UINT8 UsbEndPoint;
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UINT8 UsbAddress;
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UINT8 Reserved2;
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UINT8 Reserved3;
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}USB2_DEBUG_PORT_REGISTER;
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typedef struct _USB2_EHCI_CAPABILITY_REGISTER {
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UINT8 CapLength;
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UINT8 Reserved;
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UINT16 HciVersion;
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UINT32 HcsParams;
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UINT32 HccParams;
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UINT32 HcspPortRoute;
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}USB2_EHCI_CAPABILITY_REGISTER;
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#define USB2_EHCI_USBCMD_RUN 0x00000001
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#define USB2_EHCI_USBCMD_RESET 0x00000002
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#define USB2_EHCI_USBSTS_HC_HALTED 0x00001000
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#define USB2_EHCI_PORTSC_PORT_OWNER 0x00002000
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#define USB2_EHCI_PORTSC_PORT_POWER 0x00001000
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#define USB2_EHCI_PORTSC_PORT_RESET 0x00000100
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#define USB2_EHCI_PORTSC_PORT_SUSPEND 0x00000080
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#define USB2_EHCI_PORTSC_PORT_ENABLED 0x00000004
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typedef struct _USB2_EHCI_OPERATIONAL_REGISTER {
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UINT32 UsbCommand;
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UINT32 UsbStatus;
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UINT32 UsbInterruptEnable;
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UINT32 UsbFrameIndex;
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UINT32 SegmentSelector;
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UINT32 FrameListBaseAddress;
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UINT32 NextAsyncListAddress;
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UINT32 Reserved[9];
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UINT32 ConfigFlag;
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UINT32 PortSc[0x0F];
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}USB2_EHCI_OPERATIONAL_REGISTER;
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#define USB2_DEBUG_PORT_DRIVER_BUFFER_MAX USB2_DEBUG_PORT_DEVICE_BUFFER_MAX * 2
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typedef struct _USB2_DEBUG_PORT_INSTANCE {
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UINT32 EhciCapRegister;
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UINT32 EhciOpRegister;
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UINT32 PortSc;
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UINT32 DebugRegister;
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BOOLEAN Ready;
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UINT8 PciBusNumber;
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UINT8 PciDeviceNumber;
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UINT8 PciDeviceFunction;
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UINT8 Reserved1;
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UINT8 BarIndex;
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UINT16 BarOffset;
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UINT32 PortBase;
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UINT8 PortNumber;
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UINT8 PortAddress;
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UINT8 ReadEndpoint;
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UINT8 WriteEndpoint;
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UINT8 ReadEndpointDataToggle;
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UINT8 WriteEndpointDataToggle;
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UINT8 Reserved2[2];
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INT32 TempDataLength;
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INT32 TempDataIndex;
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UINT8 TempData[USB2_DEBUG_PORT_DRIVER_BUFFER_MAX];
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}USB2_DEBUG_PORT_INSTANCE;
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//
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// Setup Packet
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//
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// Data phase transfer direction
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//
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#define USB2_REQUEST_TYPE_HOST_TO_DEVICE 0x00
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#define USB2_REQUEST_TYPE_DEVICE_TO_HOST 0x80
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//
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// Type
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//
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#define USB2_REQUEST_TYPE_STANDARD 0x00
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#define USB2_REQUEST_TYPE_CLASS 0x20
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#define USB2_REQUEST_TYPE_VENDOR 0x40
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//
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// Recipient
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//
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#define USB2_REQUEST_TYPE_DEVICE 0x00
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#define USB2_REQUEST_TYPE_INTERFACE 0x01
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#define USB2_REQUEST_TYPE_ENDPOINT 0x02
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#define USB2_REQUEST_TYPE_OTHER 0x03
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//
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// Request
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//
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#define USB2_REQUEST_GET_STATUS 0x00
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#define USB2_REQUEST_CLEAR_FEATURE 0x01
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#define USB2_REQUEST_SET_FEATURE 0x03
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#define USB2_REQUEST_SET_ADDRESS 0x05
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#define USB2_REQUEST_GET_DESCRIPTOR 0x06
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#define USB2_REQUEST_SET_DESCRIPTOR 0x07
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#define USB2_REQUEST_GET_CONFIGURATION 0x08
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#define USB2_REQUEST_SET_CONFIGURATION 0x09
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#define USB2_REQUEST_GET_INTERFACE 0x0A
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#define USB2_REQUEST_SET_INTERFACE 0x11
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//
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// Descriptor Types
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//
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#define USB2_DESCRIPTOR_TYPE_DEVICE 0x01
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#define USB2_DESCRIPTOR_TYPE_CONFIGURATION 0x02
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#define USB2_DESCRIPTOR_TYPE_STRING 0x03
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#define USB2_DESCRIPTOR_TYPE_INTERFACE 0x04
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#define USB2_DESCRIPTOR_TYPE_ENDPOINT 0x05
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#define USB2_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06
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#define USB2_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07
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#define USB2_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08
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#define USB2_DESCRIPTOR_TYPE_OTG 0x09
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#define USB2_DESCRIPTOR_TYPE_DEBUG 0x0A
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//
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// Standard Feature Selectors
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//
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#define USB2_FEATURE_DEVICE_REMOTE_WAKEUP 0x01
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#define USB2_FEATURE_ENDPOINT_HALT 0x00
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#define USB2_FEATURE_TEST_MODE 0x02
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#define USB2_FEATURE_OTG_B_HNP_ENABLE 0x03
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#define USB2_FEATURE_OTG_A_HNP_SUPPORT 0x04
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#define USB2_FEATURE_OTG_A_ALT_HNP_SUPPORT 0x05
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#define USB2_FEATURE_DEBUG_MODE 0x06
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typedef struct _USB2_SETUP_PACKET {
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UINT8 RequestType;
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UINT8 Request;
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UINT8 Value[2];
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UINT16 Index;
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UINT16 Length_;
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}USB2_SETUP_PACKET;
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typedef struct _USB2_DEBUG_DESCRIPTOR_TYPE {
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UINT8 Length_;
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UINT8 DescriptorType;
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UINT8 DebugInEndpoint;
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UINT8 DebugOutEndpoint;
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}USB2_DEBUG_DESCRIPTOR_TYPE;
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typedef struct _USB2_ENDPOINT_DESCRIPTOR_TYPE {
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UINT8 Length_;
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UINT8 DescriptorType;
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UINT8 EndpointAddress;
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UINT8 Attributes;
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UINT16 MaxPacketSize;
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UINT8 Interval;
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}USB2_ENDPOINT_DESCRIPTOR_TYPE;
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#endif /* _USB_DEBUG_PORT_H */
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