/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _memhostchipcommon_h
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#define _memhostchipcommon_h
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#include "SysHostChipCommon.h"
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#define NODE_TO_SKT(node) (node / MAX_IMC)
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#define SKT_TO_NODE(socket, mc) ((socket << 1) | (mc & BIT0))
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#define NODE_TO_MC(node) (node % MAX_IMC)
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#define SKTMC_TO_NODE(socket, mc) ((socket * MAX_IMC) | (mc % MAX_IMC))
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#define NODECH_TO_SKTCH(node, ch) (((node % MAX_IMC)*MAX_MC_CH) + ch)
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//
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//
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//MAX_CHANNELS and DYNVAR_MAX were previously defined in MmrcProjectDefinitionsGenerated.h, but
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// now are here and must be manually updated as needed depending on MMRC tool execution (they have been
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// removed from automatic generation by the tool)
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//
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// Channels
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//
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#define MAX_CHANNELS 6
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#define DYNVAR_MAX 51
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#define MAX_IMC 2
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#define MAX_MC_CH 3 // Max channels per MC
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#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket
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#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
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#define MAX_DIMM 2 // Max DIMM per channel
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#define MAX_DIMM3 3 // Max DIMM per channel
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#define MAX_TECH 19 // Number of entries in DRAM technology table
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#define MAX_RIR 4 // Number of Rank Interleave Register rules for DDR
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#define MAX_RIR_DDRT 4 // Number of Rank Interleave Register rules for NVMDIMM
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#define MAX_RIR_WAYS 8 // Number of interleave ways for RIR for DDR
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#define TAD_RULES 8 // Number of TAD rule registers
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#define MAX_TAD_WAYS 3 // Number of interleave ways for TAD RULES
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#define SAD_RULES 24 // Number of SAD rule registers
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#define MAX_SAD_RULES 24 // Number of SAD rule registers
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#define MAX_STROBE 18 // Number of strobe groups
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#define MAX_SEEDS 10 // Maximum
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#if QR_DIMM_SUPPORT
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#define MAX_RANK_DIMM 4 // Max ranks per DIMM
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#else
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#define MAX_RANK_DIMM 2 // Max ranks per DIMM
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#endif
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#define MAX_RANK_CH 8 // Max ranks per channel
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#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
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#define SPD_MODULE_PART 18 // Number of bytes of module part - DDR3
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#define SPD_MODULE_PART_DDR4 20 // Number of bytes of module part - DDR4
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#define SAD_RULES_ADDR_RANGE 4 // Max IOT rules = 4, Total address limits (lower(4) entries each)
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// Ctl FUBs
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#define NUM_CTL_PLATFORM_GROUPS 4
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// SPD Defines
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//-----------------------------------------------------------------------------
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#pragma pack(1)
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//
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// Define the WDB line. The WDB line is like the cache line.
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//
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#define MRC_WDB_LINES 32
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#define MRC_WDB_LINE_SIZE 64
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#define CADB_LINES 16
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// Define in the Critical Section function on what to wait.
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//
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typedef enum {
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DoneAndRefDrained,
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Done,
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Immediate
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} EWaitOn;
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typedef enum {
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ssOne = 0,
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ssTwo,
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ssThree,
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ssFour,
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} TSubSequencesNumber;
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#define MAX_PHASE_IN_FINE_ADJUSTMENT 64
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#pragma pack()
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#define SKX_PCKG_TYPE 4 //CMD_CTL_DELAY_H
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#define CHIP_IOGPDLY_PSECS SKX_PCKG_TYPE
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//
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// Chip specific section of the struct CPU_CSR_ACCESS_VAR
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//
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#define CPU_CSR_ACCESS_VAR_CHIP \
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typedef enum {
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TYPE_SCF_BAR = 0,
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TYPE_PCU_BAR,
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TYPE_MEM_BAR0,
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TYPE_MEM_BAR1,
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TYPE_MEM_BAR2,
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TYPE_MEM_BAR3,
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TYPE_MEM_BAR4,
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TYPE_MEM_BAR5,
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TYPE_MEM_BAR6,
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TYPE_MEM_BAR7,
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TYPE_SBREG_BAR,
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TYPE_MAX_MMIO_BAR
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} MMIO_BARS;
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// Output structures based on scope
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#define MAX_BITS 72
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#endif // _memhostchipcommon_h
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