/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef cpuhost_h
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#define cpuhost_h
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#include "PlatformHost.h"
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#include "DataTypes.h"
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#include "SysHostChipCommon.h"
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#define inline __inline
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//
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// CPU ExtFamily/Family/Model bit[19:4] of cpuid(1)_eax
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//
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#ifndef CPU_FAMILY_HSX
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#define CPU_FAMILY_HSX 0x306F // Haswell CPU
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#endif
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#ifndef CPU_FAMILY_SKX
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#define CPU_FAMILY_SKX 0x5065 // Skylake CPU
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#endif
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#ifndef CPU_FAMILY_ICX
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#define CPU_FAMILY_ICX 0x606a // IceLake CPU
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#endif
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#ifndef CPU_FAMILY_KNH
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#define CPU_FAMILY_KNH 0x706F // KnightsHill CPU
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#endif
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//typedef INT32 CPU_STATUS; // this causes MiniBIOS build failure
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typedef int CPU_STATUS;
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#define CPU_SUCCESS 0
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#define CPU_FAILURE -1
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//
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// Reset types needed post execution
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//
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#define POST_RESET_NO_RESET 0x0
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#define POST_RESET_WARM 0x2 // bit1
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#define POST_RESET_POWERGOOD 0x4 // bit2
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#define POST_RESET_AMI 0x8 // bit3
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//
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// Max reservable TOR entries defines
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//
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#define MAX_TOR_ENTRIES_ISOC 15
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#define MAX_TOR_ENTRIES_NORMAL 17
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//
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// Error Code used for LogError()
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//
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#define ERROR_CPU_BIST 0xC0
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#define ERROR_CPU_BIST_MINOR_SOME_SOCKET 0x01
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#define ERROR_CPU_BIST_MINOR_SOME_BISTRESULTMASK 0x02
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#define ERROR_CPU_BIST_MINOR_ALL 0x03
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//
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// Error Codes used for LogError() and LogWarning()
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//
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#define WARN_CPU_BIST 0xC0
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#define WARN_CPU_BIST_MINOR_LOWER_TILE_RANGE 0x01
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#define WARN_CPU_BIST_MINOR_MIDDLE_TILE_RANGE 0x02
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#define WARN_CPU_BIST_MINOR_UPPER_TILE_RANGE 0x03
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#define WARN_CPU_BIST_MINOR_ALL 0x04
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//
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// MSR definitions
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//
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#ifndef MSR_IA32_PLATFORM_ID
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#define MSR_IA32_PLATFORM_ID 0x0017
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#endif
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#ifndef MSR_APIC_BASE
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#define MSR_APIC_BASE 0x001B
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#endif
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#ifndef MSR_EBC_FREQUENCY_ID
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#define MSR_EBC_FREQUENCY_ID 0x002C
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#endif
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#ifndef MSR_CORE_THREAD_COUNT
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#define MSR_CORE_THREAD_COUNT 0x0035
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#endif
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#ifndef MSR_SOCKET_ID
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#define MSR_SOCKET_ID 0x0039
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#endif
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#ifndef MSR_IA32_FEATURE_CONTROL
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#define MSR_IA32_FEATURE_CONTROL 0x003A
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#endif
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#ifndef VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR
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#define VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR 0x61
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#endif
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#ifndef MCAONNONNEMCACHEABLEMMIO_BIT
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#define MCAONNONNEMCACHEABLEMMIO_BIT 0x1
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#endif
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#ifndef MSR_IA32_BIOS_UPDT_TRIG
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#define MSR_IA32_BIOS_UPDT_TRIG 0x0079
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#endif
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#ifndef MSR_TRACE_HUB_STH_ACPIBAR_BASE
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#define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080
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#define B_MSR_TRACE_HUB_STH_ACPIBAR_BASE_LOCK BIT0
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#define V_MSR_TRACE_HUB_STH_ACPIBAR_BASE_MASK 0x0003FFFF
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#endif
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#ifndef PCH_TRACE_HUB_FW_BASE_ADDRESS
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#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address
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#endif
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#ifndef MSR_IA32_BIOS_SIGN_ID
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#define MSR_IA32_BIOS_SIGN_ID 0x008B
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#endif
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#ifndef MSR_PLATFORM_INFO
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#define MSR_PLATFORM_INFO 0x00CE
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#endif
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#ifndef MSR_PMG_CST_CONFIG_CONTROL
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#define MSR_PMG_CST_CONFIG_CONTROL 0x00E2
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#endif
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#ifndef MSR_PMG_IO_CAPTURE_BASE
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#define MSR_PMG_IO_CAPTURE_BASE 0x0E4
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#endif
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#ifndef MSR_MCG_CONTAIN
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#define MSR_MCG_CONTAIN 0x178
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#define B_MSR_MCG_CONTAIN_PE BIT0
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#endif
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#ifndef MSR_IA32_MCG_CAP
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#define MSR_IA32_MCG_CAP 0x179
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#define B_MSR_MCG_CAP_GCM BIT24
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#endif
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#ifndef MSR_CLOCK_FLEX_MAX
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#define MSR_CLOCK_FLEX_MAX 0x0194
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#endif
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#ifndef MSR_IA32_PERF_STS
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#define MSR_IA32_PERF_STS 0x0198
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#endif
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#ifndef MSR_IA32_PERF_CTL
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#define MSR_IA32_PERF_CTL 0x0199
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#endif
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#ifndef MSR_IA32_MISC_ENABLES
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#define MSR_IA32_MISC_ENABLES 0x01A0
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#endif
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#ifndef IA32_MISC_ENABLE
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#define IA32_MISC_ENABLE 0x01A0
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#endif
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#ifndef FAST_STRING_ENABLE_BIT
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#define FAST_STRING_ENABLE_BIT 0x1
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#endif
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#ifndef MSR_MISC_PWR_MGMT
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#define MSR_MISC_PWR_MGMT 0x01AA
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#endif
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#ifndef MSR_TURBO_POWER_CURRENT_LIMIT
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#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1AC
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#endif
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#ifndef MSR_TURBO_RATIO_LIMIT
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#define MSR_TURBO_RATIO_LIMIT 0x01AD
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#endif
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#ifndef MSR_POWER_CTRL
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#define MSR_POWER_CTRL 0x01FC
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#endif
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#ifndef MSR_NO_EVICT_MODE
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#define MSR_NO_EVICT_MODE 0x02E0
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#endif
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#ifndef MSR_IA32_MC7_CTL
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#define MSR_IA32_MC7_CTL 0x041C
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#endif
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#ifndef MSR_IA32_MC8_MISC2
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#define MSR_IA32_MC8_MISC2 0x0288
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#endif
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#ifndef MSR_PCIEXBAR
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#define MSR_PCIEXBAR 0x0300
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#endif
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#ifndef MSR_PPIN_CTL
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#define MSR_PPIN_CTL 0x004E
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#endif
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#ifndef MSR_PPIN
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#define MSR_PPIN 0x004F
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#endif
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#ifndef MSR_MC_CTL
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#define MSR_MC_CTL 0x0434
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#endif
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#define MSR_UNCORE_FREQ 0x0620
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#define MSR_UPI0_MC_STS 0x0415
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#define MSR_UPI1_MC_STS 0x0431
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#define MSR_UPI2_MC_STS 0x044d
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#ifndef MTRR_PHYS_BASE_0
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#define MTRR_PHYS_BASE_0 0x0200
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#define MTRR_PHYS_MASK_0 0x0201
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#define MTRR_PHYS_BASE_1 0x0202
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#define MTRR_PHYS_MASK_1 0x0203
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#define MTRR_PHYS_BASE_2 0x0204
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#define MTRR_PHYS_MASK_2 0x0205
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#define MTRR_PHYS_BASE_3 0x0206
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#define MTRR_PHYS_MASK_3 0x0207
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#define MTRR_PHYS_BASE_4 0x0208
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#define MTRR_PHYS_MASK_4 0x0209
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#define MTRR_PHYS_BASE_5 0x020A
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#define MTRR_PHYS_MASK_5 0x020B
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#define MTRR_PHYS_BASE_6 0x020C
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#define MTRR_PHYS_MASK_6 0x020D
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#define MTRR_PHYS_BASE_7 0x020E
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#define MTRR_PHYS_MASK_7 0x020F
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#define MTRR_FIX_64K_00000 0x0250
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#define MTRR_FIX_16K_80000 0x0258
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#define MTRR_FIX_16K_A0000 0x0259
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#define MTRR_FIX_4K_C0000 0x0268
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#define MTRR_FIX_4K_C8000 0x0269
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#define MTRR_FIX_4K_D0000 0x026A
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#define MTRR_FIX_4K_D8000 0x026B
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#define MTRR_FIX_4K_E0000 0x026C
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#define MTRR_FIX_4K_E8000 0x026D
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#define MTRR_FIX_4K_F0000 0x026E
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#define MTRR_FIX_4K_F8000 0x026F
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#define MTRR_DEF_TYPE 0x02FF
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#define MTRR_MEMORY_TYPE_UC 0x00
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#define MTRR_MEMORY_TYPE_WC 0x01
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#define MTRR_MEMORY_TYPE_WT 0x04
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#define MTRR_MEMORY_TYPE_WP 0x05
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#define MTRR_MEMORY_TYPE_WB 0x06
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#define MTRR_DEF_TYPE_E 0x0800
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#define MTRR_DEF_TYPE_FE 0x0400
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#define MTRR_PHYS_MASK_VALID 0x0800
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#endif // MTRR_PHYS_BASE_0
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#define CONFIG_TDP_MAX_LEVEL 5
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//
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// Memory-mapped APIC Offsets
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//
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#define APIC_LOCAL_APIC_ID 0x020
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#define APIC_ICR_LO 0x300
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#define APIC_ICR_HI 0x310
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#define APIC_TMR_INITIAL_CNT 0x380
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#define APIC_TMR_CURRENT_CNT 0x390
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//
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// APIC Timer runs at 133MHz and by default decrements
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// the current count register at once per two clocks.
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// t = time in milliseconds
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// c = APIC Timer Initial Value
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// c = (t * 10^(-6) sec) * (133 * 10^6 count/sec) * (1/2 clocks)
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// Notice seconds and exponents cancel out leaving count value
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// c = (t * 133 / 2)
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//
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#define APIC_TMR_1US (1 * 133 / 2)
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#define APIC_TMR_10US (10 * 133 / 2)
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#define APIC_TMR_20US (20 * 133 / 2)
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#define APIC_TMR_100US (100 * 133 / 2)
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#define APIC_TMR_200US (200 * 133 / 2)
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#define APIC_TMR_10MS (10 * 1000 * 133 / 2)
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#endif // cpuhost_h
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