/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _UNCORE_COMMON_INCLUDES_H_
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#define _UNCORE_COMMON_INCLUDES_H_
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#ifndef V_INTEL_VID
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#define V_INTEL_VID 0x8086
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#endif
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#ifndef MAX_CORE
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#define MAX_CORE 28 // Maximum cores per CPU (SKX)
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#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU
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#endif
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#define MAX_PROCESSOR_CORE_RATIO 100
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#define DEFAULT_PROCESSOR_CORE_RATIO 23
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#define MAX_SCRAMBLE_SEED_LOW 65535
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#define MAX_SCRAMBLE_SEED_HIGH 65535
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#define ITURBO_MODE_TRADITIONAL 0
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#define ITURBO_MODE_POWER_OPTIMIZED 4
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#define MAX_PROCESSOR_TSEG 5
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// Define the different SKX package Sku's
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#define SKX_PHY_CHOP_HCC 0x2
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#define SKX_PHY_CHOP_MCC 0x1
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#define SKX_PHY_CHOP_LCC 0x0
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//
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// Defines used for variables to be range checked before consumption.
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// For MiniBIOS support, these are also defined in
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// so any changes here need to be updated in these files as well.
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// If you change this, please also update CPU_FAMILY_XXX in \Library\ProcMemInit\Include\CpuPciAccess.h, Library\ProcessorStartup\Ia32\ProcessorStartupPlatform.inc
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#ifndef CPU_FAMILY_HSX
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#define CPU_FAMILY_HSX 0x306F // Haswell CPU
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#endif
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#ifndef CPU_FAMILY_SKX
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#define CPU_FAMILY_SKX 0x5065 // Skylake CPU
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#endif
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// SKX REV_ID SiliconID SteppingID CPUID ChopType
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// A0 0 0 0 0x50650 3
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// A1 0 1 0 0x50650 3
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// A2 2 2 1 0x50651 3
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// B0 3 3 2 0x50652 3
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// L0 4 4 2 0x50652 2
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// B1 5 5 3 0x50653 3
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// H0 6 6 4 0x50654 3 (xcc)
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// M0 7 6 4 0x50654 2 (hcc)
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// U0 8 6 4 0x50654 0 (lcc)
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//
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// xy_REV_SKX is the logical ID for BIOS to distinguish the Si
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// A0 and A1 still keep to 0
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//
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#ifndef A0_REV
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#define A0_REV 0x00
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#endif
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#ifndef A0_REV_SKX
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#define A0_REV_SKX A0_REV
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#endif
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#ifndef A1_REV_SKX
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#define A1_REV_SKX A0_REV
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#endif
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#ifndef A2_REV_SKX
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#define A2_REV_SKX 0x02
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#endif
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#ifndef B0_REV_SKX
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#define B0_REV_SKX 0x03
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#endif
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#ifndef L0_REV_SKX
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#define L0_REV_SKX 0x04
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#endif
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#ifndef B1_REV_SKX
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#define B1_REV_SKX 0x05
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#endif
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#ifndef H0_REV_SKX
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#define H0_REV_SKX 0x06
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#endif
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#ifndef M0_REV_SKX
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#define M0_REV_SKX 0x07
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#endif
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#ifndef U0_REV_SKX
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#define U0_REV_SKX 0x08
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#endif
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#ifndef C0_REV_SKX
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#define C0_REV_SKX 0x09
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#endif
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//
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// Xy_CPU_STEP is from CPUID
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//
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#ifndef A0_CPU_STEP
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#define A0_CPU_STEP 0x00
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#endif
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#ifndef A1_CPU_STEP
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#define A1_CPU_STEP A0_CPU_STEP
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#endif
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#ifndef A2_CPU_STEP
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#define A2_CPU_STEP 0x01
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#endif
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#ifndef B0_CPU_STEP
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#define B0_CPU_STEP 0x02
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#endif
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#ifndef L0_CPU_STEP
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#define L0_CPU_STEP 0x02
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#endif
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#ifndef B1_CPU_STEP
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#define B1_CPU_STEP 0x03
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#endif
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#ifndef H0_CPU_STEP
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#define H0_CPU_STEP 0x04
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#endif
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#ifndef M0_CPU_STEP
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#define M0_CPU_STEP 0x04
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#endif
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#ifndef U0_CPU_STEP
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#define U0_CPU_STEP 0x04
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#endif
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#ifndef C0_CPU_STEP
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#define C0_CPU_STEP 0x05
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#endif
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#include "MaxSocket.h"
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#define MAX_THREAD 2
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#define MAX_DIE 1
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#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_SOCKET)
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#ifndef MAX_HA
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#define MAX_HA 2
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#endif
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// If you change this, please also update MAX_KTI_PORTS in \Library\ProcMemInit\Platform\Include\PlatformHost.h
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#ifndef MAX_KTI_PORTS
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#define MAX_KTI_PORTS 3 // Max KTI ports supported
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#endif
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// If you change this, please also update MAX_IMC in Library\ProcMemInit\Include\MemHostChip.h
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// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
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#ifndef MAX_IMC
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#define MAX_IMC 2 // Maximum memory controllers per socket
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#endif
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// If you change this, please also update MAX_MC_CH in Library\ProcMemInit\Include\MemHostChip.h
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// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
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#ifndef MAX_MC_CH
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#define MAX_MC_CH 3 // Max number of channels per MC (3 for EP)
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#endif
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// If you change this, please also update MAX_CH in Library\ProcMemInit\Include\MemHostChip.h
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// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
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#ifndef MAX_CH
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#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
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#endif
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// If you change this, please also update MAX_DIMM in Library\ProcMemInit\Include\MemHostChip.h
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#ifndef MAX_DIMM
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#define MAX_DIMM 2 // Max DIMM per channel
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#endif
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// If you change this, please also update MC_MAX_NODE in Library\ProcMemInit\Include\MemHostChip.h
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#ifndef MC_MAX_NODE
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#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
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#endif
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// If you change this, please also update MAX_SYS_CH in Library\ProcMemInit\Include\MemHostChip.h
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// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
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#ifndef MAX_SYS_CH
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#define MAX_SYS_CH (MAX_CH * MAX_SOCKET) // Max channels in the system
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#endif
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#define MAX_SYS_DIMM MAX_SYS_CH * MAX_DIMM
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#define MAX_CRS_ENTRIES_PER_NODE 8 // Max number of ranges allowed on a memory node
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#ifndef NUMBER_PORTS_PER_SOCKET
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#define NUMBER_PORTS_PER_SOCKET 21
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#endif
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#ifndef CB3_DEVICES_PER_SOCKET
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#define CB3_DEVICES_PER_SOCKET 8
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#endif
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#ifndef TOTAL_CB3_DEVICES
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#if MAX_SOCKET > 4
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#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S.
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#else
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#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices.
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#endif
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#endif
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#ifndef MaxIIO
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#define MaxIIO MAX_SOCKET
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#endif
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#ifndef MAX_TOTAL_PORTS
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#if MAX_SOCKET > 4
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#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal
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#else
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#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO
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#endif
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#endif
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#ifndef TOTAL_IIO_STACKS
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#if MAX_SOCKET > 4
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#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure!
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#else
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#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK
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#endif
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#endif
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#ifndef NUMBER_NTB_PORTS_PER_SOCKET
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#define NUMBER_NTB_PORTS_PER_SOCKET 3
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#endif
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#ifndef MAX_NTB_PORTS
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#if MAX_SOCKET > 4
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#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#else
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#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#endif
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#endif
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#ifndef VMD_STACK_PER_SOCKET
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#define VMD_STACK_PER_SOCKET 3
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#endif
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#ifndef VMD_PORT_PER_STACK
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#define VMD_PORT_PER_STACK 4
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#endif
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#ifndef VMD_PORTS_PER_SOCKET
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#define VMD_PORTS_PER_SOCKET 12
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#endif
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#if MAX_SOCKET > 4
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#ifndef MAX_VMD_PORTS
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#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET
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#endif
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#ifndef MAX_VMD_STACKS
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#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET*/
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#endif
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#else
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#ifndef MAX_VMD_PORTS
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#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET
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#endif
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#ifndef MAX_VMD_STACKS
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#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET*/
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#endif
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#endif
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#ifndef NUM_DEVHIDE_REGS
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#define NUM_DEVHIDE_REGS 8
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#endif
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#ifndef MAX_DEVHIDE_REGS
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#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS)
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#endif
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#ifndef MAX_DEVHIDE_REGS_PER_SYSTEM
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#if MAX_SOCKET > 4
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#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MAX_SOCKET)
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#else
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#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MAX_SOCKET)
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#endif
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#endif
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#if MAX_SOCKET > 4
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#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS)
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#else
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#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS)
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#endif
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#define MAX_IOU_PORT_DEVICES 4
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//
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// Resource Ratio units used by Uncore Init PEIM.
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//
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// Assumption: these values must be 2^N; Otherwise the algorithm in OemProcMemInit.c
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// needs to be adjusted: the "if (Alignment > KTI_SOCKET_BUS_RATIO_UNIT) {" should be
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// removed when computing adjusted "Length".
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//
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#define KTI_SOCKET_BUS_RATIO_UNIT 0x20
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#define KTI_SOCKET_IO_RATIO_UNIT 0x2000
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#define KTI_SOCKET_MMIOL_RATIO_UNIT 0x4000000
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//
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// Maximum alignment bit allowed for Socket PCI Resources.
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//
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#define KTI_SOCKET_MAX_BUS_ALIGNMENT 0x8
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#define KTI_SOCKET_MAX_IO_ALIGNMENT 0x10
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#define KTI_SOCKET_MAX_MMIOL_ALIGNMENT 0x20
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#ifndef MAX_IIO_STACK
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#define IIO_CSTACK 0
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#define IIO_PSTACK0 1
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#define IIO_PSTACK1 2
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#define IIO_PSTACK2 3
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#define IIO_PSTACK3 4
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#define IIO_PSTACK4 5
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#define MAX_IIO_STACK 6
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#endif
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#ifndef UNDEFINED_RAS
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#define HEDT_RAS 0x0
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#define BASIC_RAS_AX 0x1 // Valid in A stepping only.
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#define S1WS_RAS 0x2 // Not valid in A stepping.
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#define CORE_RAS 0x3 // Not valid in A stepping .
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#define STANDARD_RAS 0x4
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#define FPGA_RAS 0x5 // Not valid in A stepping.
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#define ADVANCED_RAS 0x6
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#define UNDEFINED_RAS 0x7
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#endif
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//
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// Defines used for variables to be range checked before consumption.
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//
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#define MAX_CAS_LATENCY 32
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#define MAX_TRP_LATENCY 32
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#define MAX_TRCD_LATENCY 32
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#define MAX_TRRD_LATENCY 255
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#define MAX_TWTR_LATENCY 255
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#define MAX_TRAS_LATENCY 63
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#define MAX_TRTP_LATENCY 255
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#define MAX_TWR_LATENCY 50
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#define MAX_TFAW_LATENCY 63
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#define MAX_TCWL_LATENCY 31
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#define MAX_TRC_LATENCY 255
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#define MAX_REFRESH_RATE 32767
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#define MAX_TRFC_LATENCY 1023
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#define MAX_MC_BGF_THRESHOLD 15
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//
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// ACPI table information used to initialize tables.
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//
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#define EFI_ACPI_OEM_ID "INTEL "
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#define EFI_ACPI_OEM_TABLE_ID 0x59454C525550 // "PURLEY"
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#define EFI_ACPI_OEM_REVISION 0x00000002
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#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL"
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#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009
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#endif
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