/** @file
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This file is SampleCode for Intel SA PEI Policy initialization.
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Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "MrcOemPlatform.h"
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#include <Library/CpuPlatformLib.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/SmbusLib.h>
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#include <PchAccess.h>
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#include <Library/PeiSaPolicyLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/ConfigBlockLib.h>
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#pragma pack (push, 1)
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typedef union {
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struct {
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UINT32 : 8;
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UINT32 MAX_NON_TURBO_LIM_RATIO : 8;
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UINT32 : 16;
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UINT32 : 32;
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} Bits;
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UINT64 Data;
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UINT32 Data32[2];
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UINT16 Data16[4];
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UINT8 Data8[8];
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} PCU_CR_PLATFORM_INFO_STRUCT;
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#pragma pack (pop)
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#define SA_SYSTEM_BCLK (100)
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#define PCU_CR_PLATFORM_INFO (0xCE)
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#define MRC_POST_CODE_LOW_BYTE_ADDR (0x48)
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#define MRC_POST_CODE_HIGH_BYTE_ADDR (0x49)
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#define MAX_SPD_PAGE_COUNT (2)
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#define MAX_SPD_PAGE_SIZE (256)
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#define MAX_SPD_DDR3_SIZE (MAX_SPD_PAGE_SIZE * 1)
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#define MAX_SPD_DDR4_SIZE (MAX_SPD_PAGE_SIZE * 2)
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#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
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#define SPD_PAGE_ADDRESS_0 (0x6C)
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#define SPD_PAGE_ADDRESS_1 (0x6E)
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#define SPD_DDR3_XMP_OFFSET (176)
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#define SPD_DDR4_XMP_OFFSET (384)
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#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02)
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#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B)
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#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C)
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#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
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#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
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/**
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Read the SPD data over the SMBus, at the specified SPD address, starting at
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the specified starting offset and read the given amount of data.
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@param[in] SpdAddress - SPD SMBUS address
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@param[in, out] Buffer - Buffer to store the data.
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@param[in] Start - Starting SPD offset
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@param[in] Size - The number of bytes of data to read and also the size of the buffer.
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@param[in, out] Page - The final page that is being pointed to.
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@retval RETURN_SUCCESS if the read is successful, otherwise error status.
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**/
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static
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RETURN_STATUS
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DoSpdRead (
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IN const UINT8 SpdAddress,
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IN OUT UINT8 *const Buffer,
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IN const UINT16 Start,
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IN UINT16 Size,
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IN OUT UINT8 *const Page
|
)
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{
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RETURN_STATUS EfiStatus;
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BOOLEAN PageUpdate;
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UINT16 Count;
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UINT16 Index;
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EfiStatus = RETURN_DEVICE_ERROR;
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if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) {
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Count = 0;
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PageUpdate = FALSE;
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while (Size--) {
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Index = Start + Count;
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if ((Index / MAX_SPD_PAGE_SIZE) != *Page) {
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*Page = (UINT8) (Index / MAX_SPD_PAGE_SIZE);
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PageUpdate = TRUE;
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}
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Index %= MAX_SPD_PAGE_SIZE;
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if (PageUpdate == TRUE) {
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PageUpdate = FALSE;
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SmBusWriteDataByte ((*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, &EfiStatus);
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}
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Buffer[Count] = SmBusReadDataByte (SpdAddress | ((UINT32) Index << 8), &EfiStatus);
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if (RETURN_SUCCESS != EfiStatus) {
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Buffer[Count] = 0;
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break;
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}
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Count++;
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}
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EfiStatus = RETURN_SUCCESS;
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}
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return (EfiStatus);
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}
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/**
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See if there is valid XMP SPD data.
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@param[in] Debug - Mrc debug structure.
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@param[in, out] Spd - Mrc SPD structure.
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@param[in] XmpStart - The current offset in the SPD.
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@retval TRUE if valid, FALSE in not.
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**/
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static
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BOOLEAN
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VerifyXmp (
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IN OUT MrcSpd *const Spd,
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IN const UINT16 XmpStart
|
)
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{
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SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1;
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SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2;
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BOOLEAN Xmp;
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Xmp = FALSE;
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switch (((UINT8 *) Spd) [2]) {
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case SPD_DDR3_SDRAM_TYPE_NUMBER:
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Header1 = &Spd->Ddr3.Xmp.Header;
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if (XmpStart == ((UINT32) (Header1) - (UINT32) Spd)) {
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Xmp = TRUE;
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if ((Header1->XmpRevision.Data & 0xFE) == 0x12) {
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return (TRUE);
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} else {
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Header1->XmpId = 0;
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Header1->XmpOrgConf.Data = 0;
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Header1->XmpRevision.Data = 0;
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}
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}
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break;
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case SPD_DDR4_SDRAM_TYPE_NUMBER:
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Header2 = &Spd->Ddr4.EndUser.Xmp.Header;
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if (XmpStart == ((UINT32) (Header2) - (UINT32) Spd)) {
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Xmp = TRUE;
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if ((Header2->XmpRevision.Data) == 0x20) {
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return (TRUE);
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} else {
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Header2->XmpId = 0;
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Header2->XmpOrgConf.Data = 0;
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Header2->XmpRevision.Data = 0;
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}
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}
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break;
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case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
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case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
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return (TRUE);
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default:
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return (FALSE);
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}
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if (!Xmp) {
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return (TRUE);
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}
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return (FALSE);
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}
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/**
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Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
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The SPD data locations read is controlled by the current boot mode.
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@param[in] BootMode - The current MRC boot mode.
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@param[in] Address - SPD SmBus address offset.
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@param[in] Buffer - Buffer that contains the data read from the SPD.
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@param[in] SpdDdr3Table - Indicates which SPD bytes to read.
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@param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes.
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@param[in] SpdDdr4Table - Indicates which SPD bytes to read.
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@param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes.
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@param[in] SpdLpddrTable - Indicates which SPD bytes to read.
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@param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes.
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@retval TRUE if the read is successful, otherwise FALSE on error.
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**/
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BOOLEAN
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GetSpdData (
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IN SPD_BOOT_MODE BootMode,
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IN UINT8 Address,
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IN OUT UINT8 *Buffer,
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IN UINT8 *SpdDdr3Table,
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IN UINT32 SpdDdr3TableSize,
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IN UINT8 *SpdDdr4Table,
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IN UINT32 SpdDdr4TableSize,
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IN UINT8 *SpdLpddrTable,
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IN UINT32 SpdLpddrTableSize
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)
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{
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const SPD_OFFSET_TABLE *Tbl;
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const SPD_OFFSET_TABLE *TableSelect;
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RETURN_STATUS Status;
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UINT32 Byte;
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UINT32 Stop;
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UINT8 Page;
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Page = (UINT8) (~0);
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Status = DoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1, &Page);
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if (RETURN_SUCCESS == Status) {
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switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) {
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case SPD_DDR3_SDRAM_TYPE_NUMBER:
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case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
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default:
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TableSelect = (SPD_OFFSET_TABLE *) SpdDdr3Table;
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Stop = (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE));
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break;
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case SPD_DDR4_SDRAM_TYPE_NUMBER:
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TableSelect = (SPD_OFFSET_TABLE *) SpdDdr4Table;
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Stop = (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE));
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break;
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case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
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TableSelect = (SPD_OFFSET_TABLE *) SpdLpddrTable;
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Stop = (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE));
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break;
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}
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for (Byte = 0; (RETURN_SUCCESS == Status) && (Byte < Stop); Byte++) {
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Tbl = &TableSelect[Byte];
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if ((1 << BootMode) & Tbl->BootMode) {
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Status = DoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tbl->End - Tbl->Start + 1, &Page);
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if (Status == RETURN_SUCCESS) {
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if (SpdCold == BootMode) {
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if (FALSE == VerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) {
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break;
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}
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}
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} else {
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break;
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}
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}
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}
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}
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return ((RETURN_SUCCESS == Status) ? TRUE : FALSE);
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}
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//
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// This is from MdeModulePkg\Include\Guid\StatusCodeDataTypeDebug.h
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// Might need to be adjusted for a particular BIOS core
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//
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#ifndef EFI_STATUS_CODE_DATA_MAX_SIZE
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#define EFI_STATUS_CODE_DATA_MAX_SIZE 200
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#endif
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/**
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Output a string to the debug stream/device.
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If there is a '%' sign in the string, convert it to '%%', so that DEBUG() macro will print it properly.
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@param[in] String - The string to output.
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@retval Nothing.
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**/
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VOID
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SaDebugPrint (
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VOID *String
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)
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{
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CHAR8 Str[EFI_STATUS_CODE_DATA_MAX_SIZE];
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CHAR8 *InputStr;
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CHAR8 *OutputStr;
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UINT32 i;
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InputStr = (CHAR8 *) String;
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OutputStr = Str;
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i = 0;
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while (*InputStr != 0) {
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if (i < (EFI_STATUS_CODE_DATA_MAX_SIZE - 2)) {
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*OutputStr++ = *InputStr;
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i++;
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if (*InputStr++ == '%') {
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*OutputStr++ = '%';
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i++;
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}
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}
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}
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*OutputStr = 0; // Terminating NULL
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DEBUG ((DEBUG_ERROR, Str));
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return;
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}
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/**
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Calculate the PCI device address for the given Bus/Device/Function/Offset.
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@param[in] Bus - PCI bus
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@param[in] Device - PCI device
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@param[in] Function - PCI function
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@param[in] Offset - Offset
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@retval The PCI device address.
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**/
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UINT32
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GetPciDeviceAddress (
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IN const UINT8 Bus,
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IN const UINT8 Device,
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IN const UINT8 Function,
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IN const UINT8 Offset
|
)
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{
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return (
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((UINT32) ((Bus) & 0xFF) << 16) |
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((UINT32) ((Device) & 0x1F) << 11) |
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((UINT32) ((Function) & 0x07) << 8) |
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((UINT32) ((Offset) & 0xFF) << 0) |
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(1UL << 31));
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}
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/**
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Calculate the PCIE device address for the given Bus/Device/Function/Offset.
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@param[in] Bus - PCI bus
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@param[in] Device - PCI device
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@param[in] Function - PCI function
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@param[in] Offset - Offset
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The PCIE device address.
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@retval The PCIe device address
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**/
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UINT32
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GetPcieDeviceAddress (
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IN const UINT8 Bus,
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IN const UINT8 Device,
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IN const UINT8 Function,
|
IN const UINT8 Offset
|
)
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{
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return (
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((UINT32) Bus << 20) +
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((UINT32) Device << 15) +
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((UINT32) Function << 12) +
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((UINT32) Offset << 0));
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}
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/**
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Read specific RTC/CMOS RAM
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@param[in] Location Point to RTC/CMOS RAM offset for read
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@retval The data of specific location in RTC/CMOS RAM.
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**/
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UINT8
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PeiRtcRead (
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IN const UINT8 Location
|
)
|
{
|
UINT8 RtcIndexPort;
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UINT8 RtcDataPort;
|
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//
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// CMOS access registers (using alternative access not to handle NMI bit)
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//
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if (Location < RTC_BANK_SIZE) {
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//
|
// First bank
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//
|
RtcIndexPort = R_PCH_RTC_INDEX_ALT;
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RtcDataPort = R_PCH_RTC_TARGET_ALT;
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} else {
|
//
|
// Second bank
|
//
|
RtcIndexPort = R_PCH_RTC_EXT_INDEX_ALT;
|
RtcDataPort = R_PCH_RTC_EXT_TARGET_ALT;
|
}
|
|
IoWrite8 (RtcIndexPort, Location & RTC_INDEX_MASK);
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return IoRead8 (RtcDataPort);
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}
|
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/**
|
Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform.
|
Since RTC time is stored in BCD, convert each value to binary.
|
|
@param[out] Seconds - The current second (0-59).
|
@param[out] Minutes - The current minute (0-59).
|
@param[out] Hours - The current hour (0-23).
|
@param[out] DayOfMonth - The current day of the month (1-31).
|
@param[out] Month - The current month (1-12).
|
@param[out] Year - The current year (2000-2099).
|
|
@retval Nothing.
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**/
|
VOID
|
GetRtcTime (
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OUT UINT8 *const Seconds,
|
OUT UINT8 *const Minutes,
|
OUT UINT8 *const Hours,
|
OUT UINT8 *const DayOfMonth,
|
OUT UINT8 *const Month,
|
OUT UINT16 *const Year
|
)
|
{
|
UINT32 Timeout;
|
|
//
|
// Wait until RTC "update in progress" bit goes low.
|
//
|
Timeout = 0x0FFFFF;
|
do {
|
IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGA);
|
if ((IoRead8 (RTC_TARGET_REGISTER) & RTC_UPDATE_IN_PROGRESS) != RTC_UPDATE_IN_PROGRESS) {
|
break;
|
}
|
} while (--Timeout > 0);
|
|
if (0 == Timeout) {
|
IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGB);
|
IoWrite8 (RTC_TARGET_REGISTER, RTC_HOLD | RTC_MODE_24HOUR);
|
|
IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGA);
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IoWrite8 (RTC_TARGET_REGISTER, RTC_CLOCK_DIVIDER | RTC_RATE_SELECT);
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IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGC);
|
IoRead8 (RTC_TARGET_REGISTER);
|
|
IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGD);
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IoRead8 (RTC_TARGET_REGISTER);
|
|
IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGB);
|
IoWrite8 (RTC_TARGET_REGISTER, RTC_MODE_24HOUR);
|
}
|
//
|
// Read seconds
|
//
|
IoWrite8 (RTC_INDEX_REGISTER, RTC_SECONDS);
|
*Seconds = IoRead8 (RTC_TARGET_REGISTER);
|
|
//
|
// Read minutes
|
//
|
IoWrite8 (RTC_INDEX_REGISTER, RTC_MINUTES);
|
*Minutes = IoRead8 (RTC_TARGET_REGISTER);
|
|
//
|
// Read hours
|
//
|
IoWrite8 (RTC_INDEX_REGISTER, RTC_HOURS);
|
*Hours = IoRead8 (RTC_TARGET_REGISTER);
|
|
//
|
// Read day of month
|
//
|
IoWrite8 (RTC_INDEX_REGISTER, RTC_DAY_OF_MONTH);
|
*DayOfMonth = IoRead8 (RTC_TARGET_REGISTER);
|
|
//
|
// Read month
|
//
|
IoWrite8 (RTC_INDEX_REGISTER, RTC_MONTH);
|
*Month = IoRead8 (RTC_TARGET_REGISTER);
|
|
//
|
// Read year and add current century.
|
//
|
IoWrite8 (RTC_INDEX_REGISTER, RTC_YEAR);
|
*Year = IoRead8 (RTC_TARGET_REGISTER);
|
|
*Seconds = BCD2BINARY (*Seconds);
|
*Minutes = BCD2BINARY (*Minutes);
|
*Hours = BCD2BINARY (*Hours);
|
*DayOfMonth = BCD2BINARY (*DayOfMonth);
|
*Month = BCD2BINARY (*Month);
|
*Year = BCD2BINARY (*Year) + CENTURY_OFFSET;
|
}
|
|
/**
|
Gets CPU current time.
|
|
@param[in] GlobalData - Pointer to global MRC data struct.
|
|
@retval The current CPU time in milliseconds.
|
**/
|
UINT64
|
GetCpuTime (
|
IN VOID *GlobalData
|
)
|
{
|
MrcParameters *MrcData;
|
MrcInput *Inputs;
|
PCU_CR_PLATFORM_INFO_STRUCT Msr;
|
UINT32 TimeBase;
|
|
MrcData = (MrcParameters *) GlobalData;
|
Inputs = &MrcData->Inputs;
|
|
Msr.Data = AsmReadMsr64 (PCU_CR_PLATFORM_INFO);
|
TimeBase = (Inputs->BClkFrequency / 1000) * Msr.Bits.MAX_NON_TURBO_LIM_RATIO; //In Millisec
|
return ((TimeBase == 0) ? 0 : DivU64x32 (AsmReadTsc (), TimeBase));
|
}
|
|
/**
|
Sets the specified number of memory words, a word at a time, at the
|
specified destination.
|
|
@param[in, out] Dest - Destination pointer.
|
@param[in] NumWords - The number of dwords to set.
|
@param[in] Value - The value to set.
|
|
@retval Pointer to the buffer.
|
**/
|
VOID *
|
SetMemWord (
|
IN OUT VOID *Dest,
|
IN UINTN NumWords,
|
IN const UINT16 Value
|
)
|
{
|
UINT16 *Buffer;
|
|
Buffer = (UINT16 *) Dest;
|
while (0 != NumWords--) {
|
*Buffer++ = Value;
|
}
|
|
return (Dest);
|
}
|
|
/**
|
Sets the specified number of memory dwords, a dword at a time, at the
|
specified destination.
|
|
@param[in, out] Dest - Destination pointer.
|
@param[in] NumDwords - The number of dwords to set.
|
@param[in] Value - The value to set.
|
|
@retval Pointer to the buffer.
|
**/
|
VOID *
|
SetMemDword (
|
IN OUT VOID *Dest,
|
IN UINT32 NumDwords,
|
IN const UINT32 Value
|
)
|
{
|
UINT32 *Buffer;
|
|
Buffer = (UINT32 *) Dest;
|
while (0 != NumDwords--) {
|
*Buffer++ = Value;
|
}
|
|
return (Dest);
|
}
|
|
|
/**
|
Gets the current memory voltage (VDD).
|
|
@param[in] GlobalData - Pointer to global MRC data struct.
|
@param[in] DefaultVdd - Default Vdd for the given platform.
|
|
@retval The current memory voltage (VDD), in millivolts. 0 means platform default.
|
**/
|
UINT32
|
GetMemoryVdd (
|
IN VOID *GlobalData,
|
IN UINT32 DefaultVdd
|
)
|
{
|
MrcParameters *MrcData;
|
UINT32 CurrentVoltage;
|
|
MrcData = (MrcParameters *) GlobalData;
|
CurrentVoltage = DefaultVdd;
|
|
return CurrentVoltage;
|
}
|
|
/**
|
Sets the memory voltage (VDD) to the specified value.
|
|
@param[in] GlobalData - Pointer to global MRC data struct.
|
@param[in] DefaultVdd - Default Vdd for the given platform.
|
@param[in] Voltage - The new memory voltage to set.
|
|
@retval The actual memory voltage (VDD), in millivolts, that is closest to what the caller passed in.
|
**/
|
UINT32
|
SetMemoryVdd (
|
IN VOID *GlobalData,
|
IN UINT32 DefaultVdd,
|
IN UINT32 Voltage
|
)
|
{
|
MrcParameters *MrcData;
|
|
MrcData = (MrcParameters *) GlobalData;
|
|
return Voltage;
|
}
|
|
/**
|
This function is used by the OEM to do a dedicated task during the MRC.
|
|
@param[in] GlobalData - include all the MRC data
|
@param[in] OemStatusCommand - A command that indicates the task to perform.
|
@param[in] Pointer - general ptr for general use.
|
|
@retval The status of the task.
|
**/
|
MrcStatus
|
CheckPoint (
|
IN VOID *GlobalData,
|
IN MrcOemStatusCommand OemStatusCommand,
|
IN VOID *Pointer
|
)
|
{
|
const SA_MEMORY_FUNCTIONS *SaCall;
|
MrcParameters *MrcData;
|
MrcInput *Inputs;
|
MrcStatus Status;
|
SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
|
MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
|
EFI_STATUS Status1;
|
|
//
|
// Locate SiPreMemPolicyPpi to do a GetConfigBlock() to access platform data
|
//
|
Status1 = PeiServicesLocatePpi (
|
&gSiPreMemPolicyPpiGuid,
|
0,
|
NULL,
|
(VOID **) &SiPreMemPolicyPpi
|
);
|
ASSERT_EFI_ERROR (Status1);
|
|
Status1 = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
|
ASSERT_EFI_ERROR (Status1);
|
MrcData = (MrcParameters *) GlobalData;
|
Inputs = &MrcData->Inputs;
|
SiPreMemPolicyPpi = (SI_PREMEM_POLICY_PPI *) Inputs->SiPreMemPolicyPpi;
|
SaCall = &MemConfigNoCrc->MrcCall;
|
Status = mrcSuccess;
|
|
switch (OemStatusCommand) {
|
case OemAfterNormalMode:
|
SaCall->MrcThermalOverrides (MrcData);
|
break;
|
|
default:
|
break;
|
}
|
|
return (mrcSuccess);
|
}
|
|
/**
|
Typically used to display to the I/O port 80h.
|
|
@param[in] GlobalData - Mrc Global Data
|
@param[in] DisplayDebugNumber - the number to display on port 80.
|
|
@retval Nothing.
|
**/
|
VOID
|
DebugHook (
|
IN VOID *GlobalData,
|
UINT16 DisplayDebugNumber
|
)
|
{
|
MrcParameters *MrcData;
|
MrcOutput *Outputs;
|
MrcDebug *Debug;
|
EFI_STATUS Status;
|
SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
|
SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
|
|
MrcData = (MrcParameters *) GlobalData;
|
Outputs = &MrcData->Outputs;
|
Debug = &Outputs->Debug;
|
|
Debug->PostCode[MRC_POST_CODE] = DisplayDebugNumber;
|
IoWrite16 (0x80, DisplayDebugNumber);
|
DEBUG ((DEBUG_INFO, "Post Code: %04Xh\n", DisplayDebugNumber));
|
|
//
|
// Locate SiPreMemPolicyPpi to do a GetConfigBlock() to access platform data
|
//
|
Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
|
ASSERT_EFI_ERROR (Status);
|
if (Status == EFI_SUCCESS) {
|
Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
|
}
|
return;
|
}
|
|
/**
|
Hook to take any action after returning from MrcStartMemoryConfiguration()
|
and prior to taking any action regarding MrcStatus. Pre-populated with issuing
|
Intel Silicon View Technology (ISVT) checkpoint 0x10.
|
|
@param[in] GlobalData - Mrc Global Data
|
@param[in] MrcStatus - Mrc status variable
|
**/
|
void
|
ReturnFromSmc (
|
IN VOID *GlobalData,
|
IN UINT32 MrcStatus
|
)
|
{
|
return;
|
}
|
|
/**
|
Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
|
|
@param[in] PciEBaseAddress - PCI express base address.
|
@param[in] ResetValue - desired value of DRAM_RESET#. 1 - reset deasserted, 0 - reset asserted.
|
**/
|
VOID
|
SaDramReset (
|
IN UINT32 PciEBaseAddress,
|
IN UINT32 ResetValue
|
)
|
{
|
UINT32 MmioBase;
|
UINT32 PmCfg2;
|
|
//
|
// Get the PCH PWRM Base
|
//
|
PchPwrmBaseGet (&MmioBase);
|
|
//
|
// Set DRAM RESET# value via PCH register (both SKL PCH-H and SKL PCH-LP)
|
//
|
PmCfg2 = MmioRead32 (MmioBase + R_PCH_PWRM_CFG2);
|
PmCfg2 &= ~(B_PCH_PWRM_CFG2_DRAM_RESET_CTL);
|
PmCfg2 |= (ResetValue << 26);
|
MmioWrite32 (MmioBase + R_PCH_PWRM_CFG2, PmCfg2);
|
|
return;
|
}
|
|
