/** @file
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The GUID definition for SaConfigHob
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SA_CONFIG_HOB_H_
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#define _SA_CONFIG_HOB_H_
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#include <SaAccess.h>
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#include <Base.h>
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extern EFI_GUID gSaConfigHobGuid;
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#pragma pack (push,1)
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///
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/// DPR Directory Types
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///
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typedef enum {
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EnumDprDirectoryTxt = 0,
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EnumDprDirectoryBiosGuard
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} DPR_DIRECTORY_ELEMENT;
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#define DPR_DIRECTORY_TYPE_TXT 0x01
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#define DPR_DIRECTORY_TYPE_BIOSGUARD 0x02
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#define DPR_DIRECTORY_MAX 2
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#define SA_VTD_ENGINE_NUMBER 2
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///
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/// DPR directory entry definition
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///
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typedef struct {
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UINT8 Type; ///< DPR Directory Type
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UINT8 Size; ///< DPR Size in MB
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UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear)
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UINT16 Reserved; ///< Must be 0
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} DPR_DIRECTORY_ENTRY;
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///
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/// The data elements should be initialized by a Platform Module.
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/// The data structure is for VT-d driver initialization
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///
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typedef struct {
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BOOLEAN VtdDisable; ///< 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table
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UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field is used to describe the base addresses for VT-d function
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BOOLEAN X2ApicOptOut; ///< This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. <b>1=Enable/Set</b> and 0=Disable/Clear
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BOOLEAN InterruptRemappingSupport; ///< This field is used to indicate Interrupt Remapping supported or not
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} SA_VTD_CONFIGURATION_HOB;
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///
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/// SA GPIO Data Structure
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///
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typedef struct {
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UINT8 ExpanderNo; ///< =Expander No For I2C based GPIO
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UINT32 GpioNo; ///< GPIO pad
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BOOLEAN Active; ///< 0=Active Low; 1=Active High
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} SA_GPIO;
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///
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/// SA PCIE RTD3 GPIO Data Structure
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///
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typedef struct {
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UINT8 GpioSupport; ///< 0=Not Supported; 1=PCH based; 2=I2C Based
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SA_GPIO HoldRst; ///< Offset 8 This field contain PCIe HLD RESET GPIO value and level information
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SA_GPIO PwrEnable; ///< This field contain PCIe PWR Enable GPIO value and level information
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UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 Device Wake GPIO number
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} PCIE_RTD3_GPIO;
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///
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/// SG Info HOB
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///
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typedef struct {
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SG_MODE SgMode;
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UINT8 RootPortDev;
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UINT8 RootPortFun;
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PCIE_RTD3_GPIO Rtd3Pcie0Gpio;
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PCIE_RTD3_GPIO Rtd3Pcie1Gpio;
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PCIE_RTD3_GPIO Rtd3Pcie2Gpio;
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UINT16 DelayAfterPwrEn;
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UINT16 DelayAfterHoldReset;
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} SA_RTD3;
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///
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/// System Agent Config Hob
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///
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaConfigHobGuid
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DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX]; ///< DPR directory entry definition
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BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
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SA_RTD3 SaRtd3; ///< SG Info HOB
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UINT8 ApertureSize; ///< Aperture size value
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UINT8 ImguAcpiMode; ///< IMGU ACPI mode: 0=Disabled, 1=IGFX Child device, 2=ACPI device
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SA_VTD_CONFIGURATION_HOB VtdData; ///< VT-d Data HOB
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BOOLEAN CridEnable; ///< This field inidicates if CRID is enabled or disabled (to support Intel(R) SIPP)
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BOOLEAN SkipPamLock; ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
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UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN]; ///< PCIe power down unused bundles support
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UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///< PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B)
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} SA_CONFIG_HOB;
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#pragma pack (pop)
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#endif
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