/** @file
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Macros to simplify and abstract the interface to PCI configuration.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SAACCESS_H_
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#define _SAACCESS_H_
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#include "SaRegs.h"
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///
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/// SystemAgent Base Address definition
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///
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#ifndef STALL_ONE_MICRO_SECOND
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#define STALL_ONE_MICRO_SECOND 1
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#endif
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#ifndef STALL_ONE_MILLI_SECOND
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#define STALL_ONE_MILLI_SECOND 1000
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#endif
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//
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// SA PCI Express* Port configuration
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//
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#define SA_PEG_BUS_NUM 0x00
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#define SA_PEG_DEV_NUM 0x01
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#define SA_PEG10_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG10_FUN_NUM 0x00
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#define SA_PEG11_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG11_FUN_NUM 0x01
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#define SA_PEG12_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG12_FUN_NUM 0x02
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#define SA_PEG_MAX_FUN 0x03
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///
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/// SgMode settings
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///
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typedef enum {
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SgModeDisabled = 0,
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SgModeReserved,
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SgModeMuxless,
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SgModeDgpu,
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SgModeMax
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} SG_MODE;
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#endif
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