/** @file
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Thermal policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _THERMAL_CONFIG_H_
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#define _THERMAL_CONFIG_H_
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#define THERMAL_CONFIG_REVISION 1
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extern EFI_GUID gThermalConfigGuid;
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#pragma pack (push,1)
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/**
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This structure lists PCH supported throttling register setting for custimization.
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When the SuggestedSetting is enabled, the customized values are ignored.
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**/
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typedef struct {
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UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
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UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
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UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
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UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
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/**
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When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
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If SuggestedSetting is used, this setting is ignored.
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**/
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UINT32 TTState13Enable : 1;
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/**
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When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
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If SuggestedSetting is used, this setting is ignored.
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**/
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UINT32 TTLock : 1;
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UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
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/**
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ULT processors support thermal management and cross thermal throttling between the processor package
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and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH
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thermal status to the processor which is factored into the processor throttling.
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Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
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**/
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UINT32 PchCrossThrottling : 1;
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UINT32 Rsvd0; ///< Reserved bytes
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} THERMAL_THROTTLE_LEVELS;
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/**
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This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
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When the SuggestedSetting is enabled, the customized values are ignored.
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**/
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typedef struct {
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UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
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UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
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UINT32 RsvdBits0 : 6; ///< Reserved bits
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UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Width
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UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Width
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UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Width
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UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Width
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UINT32 RsvdBits1 : 16; ///< Reserved bits
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} DMI_HW_WIDTH_CONTROL;
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/**
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This structure lists PCH supported SATA thermal throttling register setting for custimization.
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The settings is programmed through SATA Index/Data registers.
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When the SuggestedSetting is enabled, the customized values are ignored.
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**/
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typedef struct {
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UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
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UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
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UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
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UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
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UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
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UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
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UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
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UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
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UINT32 P0Tinact : 2; ///< Port 0 Tinactive
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UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
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UINT32 P1Tinact : 2; ///< Port 1 Tinactive
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UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
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UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
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UINT32 RsvdBits0 : 9; ///< Reserved bits
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} SATA_THERMAL_THROTTLE;
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/**
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This structure configures PCH memory throttling thermal sensor GPIO PIN settings
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**/
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typedef struct {
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/**
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GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
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When enabled, RC will overrides the selected GPIO native mode.
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For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
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For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
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For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.
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**/
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UINT32 PmsyncEnable : 1;
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UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b>
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UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary
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UINT32 RsvdBits0 : 29;
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} TS_GPIO_PIN_SETTING;
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enum PCH_PMSYNC_GPIO_X_SELECTION {
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TsGpioC,
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TsGpioD,
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MaxTsGpioPin
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};
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/**
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This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
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**/
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typedef struct {
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/**
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This will enable PCH memory throttling.
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While this policy is enabled, must also enable EnableExtts in SA policy.
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<b>0: Disable</b>; 1: Enable
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**/
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UINT32 Enable : 1;
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UINT32 RsvdBits0 : 31;
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/**
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GPIO_C and GPIO_D selection for memory throttling.
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It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature,
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and route EXTTS# accordingly.
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**/
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TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
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} PCH_MEMORY_THROTTLING;
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/**
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The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This field reports the status of Thermal Device. When it reports ThermalDevice
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is disabled, the PCI configuration space of thermal device will be hidden by
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setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST.
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**/
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UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled in PCI mode</b>, 2: Enabled in ACPI mode
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UINT32 TsmicLock : 1; ///< This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1: <b>Enabled</b>.
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UINT32 RsvdBits0 : 29;
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/**
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This field decides the settings of Thermal throttling. When the Suggested Setting
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is enabled, PCH RC will use the suggested representative values.
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**/
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THERMAL_THROTTLE_LEVELS TTLevels;
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/**
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This field decides the settings of DMI throttling. When the Suggested Setting
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is enabled, PCH RC will use the suggested representative values.
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**/
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DMI_HW_WIDTH_CONTROL DmiHaAWC;
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/**
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This field decides the settings of Sata thermal throttling. When the Suggested Setting
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is enabled, PCH RC will use the suggested representative values.
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**/
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SATA_THERMAL_THROTTLE SataTT;
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/**
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Memory Thermal Management settings
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**/
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PCH_MEMORY_THROTTLING MemoryThrottling;
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/**
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This field decides the temperature, default is <b>zero</b>.
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- 0x00 is the hottest
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- 0x1FF is the lowest temperature
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**/
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UINT16 PchHotLevel;
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UINT8 Rsvd0[6];
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} PCH_THERMAL_CONFIG;
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#pragma pack (pop)
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#endif // _THERMAL_CONFIG_H_
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