/** @file
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DMI policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _DMI_CONFIG_H_
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#define _DMI_CONFIG_H_
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#define DMI_CONFIG_REVISION 2
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extern EFI_GUID gDmiConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Add LegacyIoLowLatency support.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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0: Disable; <b>1: Enable</b> ASPM on PCH side of the DMI Link.
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While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value.
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**/
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UINT32 DmiAspm : 1;
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UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
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/**
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Set to enable low latenc of legacy IO.
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Some systems require lower IO latency irrespective of power.
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This is a tradeoff between power and IO latency.
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@note: Once this is enabled, DmiAspm is forced to disabled and so do Pcie DmiAspm in SystemAgent.
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<b>0:Disable</b>, 1:Enable
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**/
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UINT32 LegacyIoLowLatency : 1;
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UINT32 Rsvdbits : 29; ///< Reserved bits
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} PCH_DMI_CONFIG;
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#pragma pack (pop)
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#endif // _DMI_CONFIG_H_
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