/** @file
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This file provide services for DXE phase policy default initialization
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Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "DxeSaPolicyLibrary.h"
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#include <Library/ConfigBlockLib.h>
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GLOBAL_REMOVE_IF_UNREFERENCED PCIE_ASPM_OVERRIDE_LIST mPcieAspmDevsOverride[] = {
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{0x8086, 0x108b, 0xff, 2, 2}, ///< Tekoa w/o iAMT
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{0x8086, 0x108c, 0x00, 0, 0}, ///< Tekoa A2
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{0x8086, 0x108c, 0xff, 2, 2}, ///< Tekoa others
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{0x8086, 0x109a, 0xff, 2, 2}, ///< Vidalia
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{0x8086, 0x4222, 0xff, 2, 3}, ///< 3945ABG
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{0x8086, 0x4227, 0xff, 2, 3}, ///< 3945ABG
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{0x8086, 0x4228, 0xff, 2, 3}, ///< 3945ABG
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///
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/// Place structures for known bad OEM/IHV devices here
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///
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{SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} ///< End of table
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};
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GLOBAL_REMOVE_IF_UNREFERENCED PCIE_LTR_DEV_INFO mPcieLtrDevsOverride[] = {
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///
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/// Place holder for PCIe devices with correct LTR requirements
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///
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{SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} ///< End of table
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};
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extern EFI_GUID gGraphicsDxeConfigGuid;
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extern EFI_GUID gMemoryDxeConfigGuid;
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extern EFI_GUID gMiscDxeConfigGuid;
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extern EFI_GUID gPcieDxeConfigGuid;
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extern EFI_GUID gVbiosDxeConfigGuid;
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/**
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This function prints the SA DXE phase policy.
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@param[in] SaPolicy - SA DXE Policy protocol
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**/
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VOID
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SaPrintPolicyProtocol (
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IN SA_POLICY_PROTOCOL *SaPolicy
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)
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{
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EFI_STATUS Status;
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GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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MISC_DXE_CONFIG *MiscDxeConfig;
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MEMORY_DXE_CONFIG *MemoryDxeConfig;
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VBIOS_DXE_CONFIG *VbiosDxeConfig;
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//
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// Get requisite IP Config Blocks which needs to be used here
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//
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Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VOID *)&PcieDxeConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SaPolicy, &gMemoryDxeConfigGuid, (VOID *)&MemoryDxeConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SaPolicy, &gVbiosDxeConfigGuid, (VOID *)&VbiosDxeConfig);
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ASSERT_EFI_ERROR (Status);
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DEBUG_CODE_BEGIN ();
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INTN i;
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DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n"));
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DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision));
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ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION);
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DEBUG ((DEBUG_INFO, "------------------------ SA_MEMORY_CONFIGURATION -----------------\n"));
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DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS));
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for (i = 0; i < SA_MC_MAX_SOCKETS; i++) {
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DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG ((DEBUG_INFO, " ChannelASlotMap : %x\n", MemoryDxeConfig->ChannelASlotMap));
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DEBUG ((DEBUG_INFO, " ChannelBSlotMap : %x\n", MemoryDxeConfig->ChannelBSlotMap));
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DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n", MemoryDxeConfig->MrcTimeMeasure));
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DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n", MemoryDxeConfig->MrcFastBoot));
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DEBUG ((DEBUG_INFO, "------------------------ SA_PCIE_CONFIGURATION -----------------\n"));
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DEBUG ((DEBUG_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN));
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for (i = 0; i < SA_PEG_MAX_FUN; i++) {
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DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspm[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG ((DEBUG_INFO, " PegAspmL0s[%d] :", SA_PEG_MAX_FUN));
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for (i = 0; i < SA_PEG_MAX_FUN; i++) {
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DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspmL0s[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :", SA_PEG_MAX_FUN));
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for (i = 0; i < SA_PEG_MAX_FUN; i++) {
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DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegRootPortHPE[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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if (PcieDxeConfig->PcieAspmDevsOverride != NULL) {
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DEBUG ((DEBUG_INFO, "------------------------ PCIE_ASPM_OVERRIDE_LIST -----------------\n"));
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DEBUG ((DEBUG_INFO, " VendorId DeviceId RevId RootApmcMask EndpointApmcMask\n"));
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i = 0;
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while ((PcieDxeConfig->PcieAspmDevsOverride[i].VendorId != SA_PCIE_DEV_END_OF_TABLE) &&
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(i < MAX_PCIE_ASPM_OVERRIDE)) {
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DEBUG ((DEBUG_INFO, " %04x %04x %02x %01x %01x\n",
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PcieDxeConfig->PcieAspmDevsOverride[i].VendorId,
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PcieDxeConfig->PcieAspmDevsOverride[i].DeviceId,
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PcieDxeConfig->PcieAspmDevsOverride[i].RevId,
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PcieDxeConfig->PcieAspmDevsOverride[i].RootApmcMask,
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PcieDxeConfig->PcieAspmDevsOverride[i].EndpointApmcMask));
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i++;
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}
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DEBUG ((DEBUG_INFO, "------------------------ END_OF_TABLE -----------------------\n"));
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}
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if (PcieDxeConfig->PcieLtrDevsOverride != NULL) {
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DEBUG ((DEBUG_INFO, "------------------------ PCIE_LTR_DEV_INFO -----------------\n"));
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DEBUG ((DEBUG_INFO, " VendorId DeviceId RevId SnoopLatency NonSnoopLatency\n"));
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i = 0;
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while ((PcieDxeConfig->PcieLtrDevsOverride[i].VendorId != SA_PCIE_DEV_END_OF_TABLE) &&
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(i < MAX_PCIE_LTR_OVERRIDE)) {
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DEBUG ((DEBUG_INFO, " %04x %04x %02x %01x %01x\n",
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PcieDxeConfig->PcieLtrDevsOverride[i].VendorId,
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PcieDxeConfig->PcieLtrDevsOverride[i].DeviceId,
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PcieDxeConfig->PcieLtrDevsOverride[i].RevId,
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PcieDxeConfig->PcieLtrDevsOverride[i].SnoopLatency,
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PcieDxeConfig->PcieLtrDevsOverride[i].NonSnoopLatency));
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i++;
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}
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DEBUG ((DEBUG_INFO, "------------------------ END_OF_TABLE ----------------------\n"));
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}
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for (i = 0; i < SA_PEG_MAX_FUN; i++) {
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DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].LtrEnable : %x\n", i, PcieDxeConfig->PegPwrOpt[i].LtrEnable));
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DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].LtrMaxSnoopLatency : %x\n", i, PcieDxeConfig->PegPwrOpt[i].LtrMaxSnoopLatency));
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DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].ObffEnable : %x\n", i, PcieDxeConfig->PegPwrOpt[i].ObffEnable));
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DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].LtrMaxNoSnoopLatency : %x\n", i, PcieDxeConfig->PegPwrOpt[i].LtrMaxNoSnoopLatency));
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}
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if (VbiosDxeConfig != NULL) {
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DEBUG ((DEBUG_INFO, "------------------------ SA_SG_VBIOS_CONFIGURATION -----------------\n"));
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DEBUG ((DEBUG_INFO, " LoadVbios : %x\n", VbiosDxeConfig->LoadVbios));
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DEBUG ((DEBUG_INFO, " ExecuteVbios : %x\n", VbiosDxeConfig->ExecuteVbios));
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DEBUG ((DEBUG_INFO, " VbiosSource : %x\n", VbiosDxeConfig->VbiosSource));
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}
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DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n"));
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DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio));
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DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n"));
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DEBUG_CODE_END ();
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return;
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}
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EFI_STATUS
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EFIAPI
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LoadIgdDxeDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
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GraphicsDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Name = %g\n", &GraphicsDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", GraphicsDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// Initialize the Graphics configuration
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///
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GraphicsDxeConfig->PlatformConfig = 1;
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GraphicsDxeConfig->AlsEnable = 2;
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GraphicsDxeConfig->BacklightControlSupport = 2;
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GraphicsDxeConfig->IgdBlcConfig = 2;
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GraphicsDxeConfig->IgdDvmtMemSize = 1;
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GraphicsDxeConfig->GfxTurboIMON = 31;
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///
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/// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle Mapping Table
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/// Possible 20 entries (example used 11), each 16 bits as follows:
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/// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
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///
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GraphicsDxeConfig->BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///< 0%
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GraphicsDxeConfig->BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///< 10%
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GraphicsDxeConfig->BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///< 20%
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GraphicsDxeConfig->BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///< 30%
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GraphicsDxeConfig->BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///< 40%
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GraphicsDxeConfig->BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT); ///< 50%
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GraphicsDxeConfig->BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///< 60%
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GraphicsDxeConfig->BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///< 70%
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GraphicsDxeConfig->BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///< 80%
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GraphicsDxeConfig->BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///< 90%
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GraphicsDxeConfig->BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///< 100%
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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LoadPcieDxeDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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UINT8 pegFn;
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UINT8 Index;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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PcieDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Name = %g\n", &PcieDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PcieDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// Initialize the PCIE Configuration
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/// PEG ASPM per port configuration. 4 PEG controllers i.e. 0,1,2,3
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///
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for (pegFn = 0; pegFn < SA_PEG_MAX_FUN; pegFn++) {
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PcieDxeConfig->PegAspm[pegFn] = PcieAspmAutoConfig;
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PcieDxeConfig->PegAspmL0s[pegFn] = 0;
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}
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for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
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PcieDxeConfig->PegPwrOpt[Index].LtrEnable = 1;
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PcieDxeConfig->PegPwrOpt[Index].LtrMaxSnoopLatency = V_SA_LTR_MAX_SNOOP_LATENCY_VALUE;
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PcieDxeConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency = V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE;
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PcieDxeConfig->PegPwrOpt[Index].ObffEnable = 1;
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}
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PcieDxeConfig->PcieAspmDevsOverride = mPcieAspmDevsOverride;
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PcieDxeConfig->PcieLtrDevsOverride = mPcieLtrDevsOverride;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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LoadMiscDxeDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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MISC_DXE_CONFIG *MiscDxeConfig;
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MiscDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "MiscDxeConfig->Header.GuidHob.Name = %g\n", &MiscDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "MiscDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MiscDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// RMRR Base and Limit Address for USB
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///
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MiscDxeConfig->RmrrUsbBaseAddress = AllocateZeroPool (sizeof (EFI_PHYSICAL_ADDRESS) * 2);
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ASSERT (MiscDxeConfig->RmrrUsbBaseAddress != NULL);
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if (MiscDxeConfig->RmrrUsbBaseAddress != NULL) {
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///
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/// BIOS must update USB RMRR base address
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///
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MiscDxeConfig->RmrrUsbBaseAddress[0] = 0;
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MiscDxeConfig->RmrrUsbBaseAddress[1] = 0;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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LoadMemoryDxeDefault (
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IN VOID *ConfigBlockPointer
|
)
|
{
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MEMORY_DXE_CONFIG *MemoryDxeConfig;
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MemoryDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Name = %g\n", &MemoryDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MemoryDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// Initialize the Memory Configuration
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///
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///
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/// DIMM SMBus addresses info
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/// Refer to the SpdAddressTable[] mapping rule in DxeSaPolicyLibrary.h
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///
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MemoryDxeConfig->SpdAddressTable = AllocateZeroPool (sizeof (UINT8) * 4);
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ASSERT (MemoryDxeConfig->SpdAddressTable != NULL);
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if (MemoryDxeConfig->SpdAddressTable != NULL) {
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MemoryDxeConfig->SpdAddressTable[0] = DIMM_SMB_SPD_P0C0D0;
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MemoryDxeConfig->SpdAddressTable[1] = DIMM_SMB_SPD_P0C0D1;
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MemoryDxeConfig->SpdAddressTable[2] = DIMM_SMB_SPD_P0C1D0;
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MemoryDxeConfig->SpdAddressTable[3] = DIMM_SMB_SPD_P0C1D1;
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}
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MemoryDxeConfig->ChannelASlotMap = 0x01;
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MemoryDxeConfig->ChannelBSlotMap = 0x01;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
|
LoadVbiosDxeDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
VBIOS_DXE_CONFIG *VbiosDxeConfig;
|
|
VbiosDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "VbiosDxeConfig->Header.GuidHob.Name = %g\n", &VbiosDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "VbiosDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", VbiosDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// Initialize the SG VBIOS DXE Policies
|
///
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///
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/// 1 = secondary display device VBIOS Source is PCI Card
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/// 0 = secondary display device VBIOS Source is FW Volume
|
///
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VbiosDxeConfig->VbiosSource = 1;
|
return EFI_SUCCESS;
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}
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/**
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LoadSaDxeConfigBlockDefault - Initialize default settings for each SA Config block
|
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@param[in] ConfigBlockPointer The buffer pointer that will be initialized as specific config block
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@param[in] BlockId Request to initialize defaults of specified config block by given Block ID
|
|
@retval EFI_SUCCESS The given buffer has contained the defaults of requested config block
|
@retval EFI_NOT_FOUND Block ID is not defined so no default Config block will be initialized
|
**/
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EFI_STATUS
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EFIAPI
|
LoadSaDxeConfigBlockDefault (
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IN VOID *ConfigBlockPointer,
|
IN EFI_GUID BlockGuid
|
)
|
{
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if (CompareGuid (&BlockGuid, &gGraphicsDxeConfigGuid)) {
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LoadIgdDxeDefault (ConfigBlockPointer);
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} else if (CompareGuid (&BlockGuid, &gMiscDxeConfigGuid)) {
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LoadMiscDxeDefault (ConfigBlockPointer);
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} else if (CompareGuid (&BlockGuid, &gPcieDxeConfigGuid)) {
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LoadPcieDxeDefault (ConfigBlockPointer);
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} else if (CompareGuid (&BlockGuid, &gMemoryDxeConfigGuid)) {
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LoadMemoryDxeDefault (ConfigBlockPointer);
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} else if (CompareGuid (&BlockGuid, &gVbiosDxeConfigGuid)) {
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LoadVbiosDxeDefault (ConfigBlockPointer);
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} else {
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return EFI_NOT_FOUND;
|
}
|
return EFI_SUCCESS;
|
}
|
|
|
/**
|
CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
|
It allocates and zero out buffer, and fills in the Intel default settings.
|
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@param[out] SaPolicy The pointer to get SA DXE Protocol instance
|
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@retval EFI_SUCCESS The policy default is initialized.
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@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
|
**/
|
EFI_STATUS
|
EFIAPI
|
CreateSaDxeConfigBlocks (
|
IN OUT SA_POLICY_PROTOCOL **SaPolicy
|
)
|
{
|
UINT16 TotalBlockSize;
|
UINT16 TotalBlockCount;
|
UINT16 BlockCount;
|
VOID *ConfigBlockPointer;
|
EFI_STATUS Status;
|
SA_POLICY_PROTOCOL *SaInitPolicy;
|
UINT16 RequiredSize;
|
STATIC CONFIG_BLOCK_HEADER SaDxeIpBlocks [] = {
|
{{{0, sizeof (GRAPHICS_DXE_CONFIG), 0}, {0}}, GRAPHICS_DXE_CONFIG_REVISION, 0, {0, 0}},
|
{{{0, sizeof (MEMORY_DXE_CONFIG), 0}, {0}}, MEMORY_DXE_CONFIG_REVISION, 0, {0, 0}},
|
{{{0, sizeof (MISC_DXE_CONFIG), 0}, {0}}, MISC_DXE_CONFIG_REVISION, 0, {0, 0}},
|
{{{0, sizeof (PCIE_DXE_CONFIG), 0}, {0}}, PCIE_DXE_CONFIG_REVISION, 0, {0, 0}},
|
{{{0, sizeof (VBIOS_DXE_CONFIG), 0}, {0}}, VBIOS_DXE_CONFIG_REVISION, 0, {0, 0}}
|
};
|
|
SaInitPolicy = NULL;
|
TotalBlockCount = sizeof (SaDxeIpBlocks) / sizeof (CONFIG_BLOCK_HEADER);
|
DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount));
|
|
TotalBlockSize = 0;
|
for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
|
TotalBlockSize += (UINT32) SaDxeIpBlocks[BlockCount].GuidHob.Header.HobLength;
|
DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize));
|
}
|
|
RequiredSize = sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;
|
|
Status = CreateConfigBlockTable (RequiredSize, (VOID *)&SaInitPolicy);
|
ASSERT_EFI_ERROR (Status);
|
//
|
// Initalize SklSaIpBlocks table GUID
|
//
|
CopyMem (&SaDxeIpBlocks[0].GuidHob.Name, &gGraphicsDxeConfigGuid, sizeof (EFI_GUID));
|
CopyMem (&SaDxeIpBlocks[1].GuidHob.Name, &gMemoryDxeConfigGuid, sizeof (EFI_GUID));
|
CopyMem (&SaDxeIpBlocks[2].GuidHob.Name, &gMiscDxeConfigGuid, sizeof (EFI_GUID));
|
CopyMem (&SaDxeIpBlocks[3].GuidHob.Name, &gPcieDxeConfigGuid, sizeof (EFI_GUID));
|
CopyMem (&SaDxeIpBlocks[4].GuidHob.Name, &gVbiosDxeConfigGuid, sizeof (EFI_GUID));
|
|
//
|
// Initialize Policy Revision
|
//
|
SaInitPolicy->TableHeader.Header.Revision = SA_POLICY_PROTOCOL_REVISION;
|
//
|
// Initialize ConfigBlockPointer to NULL
|
//
|
ConfigBlockPointer = NULL;
|
//
|
// Loop to identify each config block from SaDxeIpBlocks[] Table and add each of them
|
//
|
for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
|
ConfigBlockPointer = (VOID *)&SaDxeIpBlocks[BlockCount];
|
Status = AddConfigBlock ((VOID *) SaInitPolicy, (VOID *)&ConfigBlockPointer);
|
ASSERT_EFI_ERROR (Status);
|
LoadSaDxeConfigBlockDefault ((VOID *) ConfigBlockPointer, SaDxeIpBlocks[BlockCount].GuidHob.Name);
|
}
|
//
|
// Assignment for returning SaPolicy config block base address
|
//
|
*SaPolicy = SaInitPolicy;
|
return EFI_SUCCESS;
|
}
|
|
|
/**
|
SaInstallPolicyProtocol installs SA Policy.
|
While installed, RC assumes the Policy is ready and finalized. So please update and override
|
any setting before calling this function.
|
|
@param[in] ImageHandle Image handle of this driver.
|
@param[in] SaPolicy The pointer to SA Policy Protocol instance
|
|
@retval EFI_SUCCESS The policy is installed.
|
@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
|
|
**/
|
EFI_STATUS
|
EFIAPI
|
SaInstallPolicyProtocol (
|
IN EFI_HANDLE ImageHandle,
|
IN SA_POLICY_PROTOCOL *SaPolicy
|
)
|
{
|
EFI_STATUS Status;
|
|
///
|
/// Print SA DXE Policy
|
///
|
SaPrintPolicyProtocol (SaPolicy);
|
|
///
|
/// Install protocol to to allow access to this Policy.
|
///
|
Status = gBS->InstallMultipleProtocolInterfaces (
|
&ImageHandle,
|
&gSaPolicyProtocolGuid,
|
SaPolicy,
|
NULL
|
);
|
ASSERT_EFI_ERROR (Status);
|
|
return Status;
|
}
|
|
