/** @file
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This protocol provides the memory information data, such as
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total physical memory size, memory frequency, memory size
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of each dimm and rank.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _MEM_INFO_PROTOCOL_H_
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#define _MEM_INFO_PROTOCOL_H_
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gMemInfoProtocolGuid;
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//
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// Protocol definitions
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//
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#define NODE_NUM 1
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#define CH_NUM 2
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#define DIMM_NUM 2
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#define RANK_NUM 2
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#define SLOT_NUM (CH_NUM * DIMM_NUM)
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#define PROFILE_NUM 4 // number of memory profiles supported
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#define XMP_PROFILE_NUM 2 // number of XMP profiles supported
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//
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// Matches MrcDdrType enum in MRC
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//
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#ifndef MRC_DDR_TYPE_DDR4
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#define MRC_DDR_TYPE_DDR4 0
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#endif
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#ifndef MRC_DDR_TYPE_DDR3
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#define MRC_DDR_TYPE_DDR3 1
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR3
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#define MRC_DDR_TYPE_LPDDR3 2
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#endif
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 3
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#endif
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//
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// Matches MrcDimmSts enum in MRC
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//
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#ifndef DIMM_ENABLED
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#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
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#endif
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#ifndef DIMM_DISABLED
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#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
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#endif
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#ifndef DIMM_PRESENT
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#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
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#endif
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#ifndef DIMM_NOT_PRESENT
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#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
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#endif
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#pragma pack(1)
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///
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/// Memory timing Structure
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///
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typedef struct {
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UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds.
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UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's command rate mode.
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UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's CAS latency.
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UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
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UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
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UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
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UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time
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UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
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UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
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UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
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UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
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UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM's minimum write recovery time.
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UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
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UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
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UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
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UINT16 tWTR_L; ///< Offset 34 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
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UINT16 tWTR_S; ///< Offset 36 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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UINT8 Rsvd[2]; ///< Offset 38
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} MEMORY_TIMING;
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typedef struct {
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UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
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UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
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UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
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UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs
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} TURNAROUND_TIMING;
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// @todo use the MemInfoHob data instead of duplicate structure.
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///
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/// Memory information Data Structure
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///
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typedef struct {
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MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timming information for the DIMM
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UINT32 memSize; ///< Offset 128 Total physical memory size
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UINT16 ddrFreq; ///< Offset 132 DDR Current Frequency
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UINT16 ddrFreqMax; ///< Offset 134 DDR Maximum Frequency
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UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Size of each DIMM
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UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The voltage setting for the DIMM
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UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152 The enumeration value from MrcDimmSts
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UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156 No. of ranks in a dimm
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UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160 SPD data of each DIMM
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UINT8 RefClk; ///< Offset 192 Reference Clock
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UINT8 Ratio; ///< Offset 193 Clock Multiplier
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BOOLEAN EccSupport; ///< Offset 194 ECC supported or not
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UINT8 Profile; ///< Offset 195 Currently running memory profile
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UINT8 XmpProfileEnable; ///< Offset 196: 0 = no XMP DIMMs in system
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UINT8 DdrType; ///< Offset 197: Current DDR type, see DDR_TYPE_xxx defines above
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UINT8 Reserved[2]; ///< Offset 198 Reserved bytes for future use
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UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200 The Default XMP tCK values read from SPD.
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TURNAROUND_TIMING tRd2Rd[CH_NUM]; ///< Read-to-Read Turn Around Timings
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TURNAROUND_TIMING tRd2Wr[CH_NUM]; ///< Read-to-Write Turn Around Timings
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TURNAROUND_TIMING tWr2Rd[CH_NUM]; ///< Write-to-Read Turn Around Timings
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TURNAROUND_TIMING tWr2Wr[CH_NUM]; ///< Write-to-Write Turn Around Timings
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} MEMORY_INFO_DATA;
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#pragma pack()
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///
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/// Memory information Protocol definition
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///
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typedef struct {
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MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure
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} MEM_INFO_PROTOCOL;
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#endif
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