/** @file
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Switchable Graphics policy definitions
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SWITCHABLE_GRAPHICS_CONFIG_H_
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#define _SWITCHABLE_GRAPHICS_CONFIG_H_
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#define SWITCHABLE_GRAPHICS_CONFIG_REVISION 1
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#define GP_ENABLE 1
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#define GP_DISABLE 0
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#pragma pack(push, 1)
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///
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/// GPIO Support
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///
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typedef enum {
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NotSupported = 0,
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PchGpio,
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I2CGpio,
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} GPIO_SUPPORT;
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///
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/// SA GPIO Data Structure
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///
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typedef struct {
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UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO
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BOOLEAN Active; ///< Offset 1 0=Active Low; 1=Active High
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UINT8 Rsvd0[2]; ///< Offset 2 Reserved
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UINT32 GpioNo; ///< Offset 4 GPIO pad
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} SA_GPIO_INFO;
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/**
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SA PCIE RTD3 GPIO Data Structure
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**/
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typedef struct {
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SA_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RESET GPIO value and level information
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SA_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR Enable GPIO value and level information
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UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number
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UINT8 GpioSupport; ///< Offset 20 Depends on board design the GPIO configuration may be different: <b>0=Not Supported</b>, 1=PCH Based, 2=I2C based
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UINT8 Rsvd0[3]; ///< Offset 21
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} SA_PCIE_RTD3_GPIO;
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/**
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This Configuration block configures SA PCI Express 0/1/2 RTD3 GPIOs & Root Port.
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Swithable Gfx/Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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SA_PCIE_RTD3_GPIO SaRtd3Pcie0Gpio; ///< Offset 28 RTD3 GPIOs used for PCIe0
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SA_PCIE_RTD3_GPIO SaRtd3Pcie1Gpio; ///< Offset 52 RTD3 GPIOs used for PCIe1
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SA_PCIE_RTD3_GPIO SaRtd3Pcie2Gpio; ///< Offset 76 RTD3 GPIOs used for PCIe2
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UINT8 RootPortIndex; ///< Offset 124 Root Port Index number used for SG
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UINT8 Rsvd0[3]; ///< Offset 125 Reserved for DWORD Alignment
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} SWITCHABLE_GRAPHICS_CONFIG;
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#pragma pack(pop)
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#endif // _SWITCHABLE_GRAPHICS_CONFIG_H_
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