/** @file
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Policy definition for PCIe Config Block
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_PEI_PREMEM_CONFIG_H_
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#define _PCIE_PEI_PREMEM_CONFIG_H_
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#include <Library/GpioLib.h>
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#include <SaAccess.h>
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#pragma pack(push, 1)
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#define SA_PCIE_PEI_PREMEM_CONFIG_REVISION 3
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///
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/// SA GPIO Data Structure
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///
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typedef struct {
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GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
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UINT8 Value; ///< Offset 4: GPIO Value
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UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
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UINT32 Active :1; ///< Offset 8: 0=Active Low; 1=Active High
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UINT32 RsvdBits0:31;
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} SA_GPIO_INFO_PCIE;
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///
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/// SA Board PEG GPIO Info
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///
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typedef struct {
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SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin
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SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin
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BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not Supported
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UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
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} PEG_GPIO_DATA;
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/**
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PCI Express and DMI controller configuration\n
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@note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Change PegGen3RxCtleOverride of PCIE_PEI_PREMEM_CONFIG from one bit to UINT8
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- Change DmiGen3RxCtlePeaking default to 0
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<b>Revision 3</b>:
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- Added PEG IMR support
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- Added UINT8 PegImrEnable
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- Added UINT16 PegImrSize
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- Added UINT8 ImrRpSelection
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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/**
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Offset 28:0 :
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<b>(Test)</b> DMI Link Speed Control
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- <b>Auto</b> (0x0) : Maximum possible link speed (Default)
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- Gen1 (0x1) : Limit Link to Gen1 Speed
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- Gen2 (0x2) : Limit Link to Gen2 Speed
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- Gen3 (0x3) : Limit Link to Gen3 Speed
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**/
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UINT32 DmiMaxLinkSpeed : 2;
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/**
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Offset 28:2 :
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<b>(Test)</b> DMI Equalization Phase 2 Enable Control
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- Disabled (0x0) : Disable phase 2
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- Enabled (0x1) : Enable phase 2
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- <b>Auto</b> (0x2) : Use the current default method (Default)
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**/
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UINT32 DmiGen3EqPh2Enable : 2;
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/**
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Offset 28:4 :
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<b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
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- <b>Auto</b> (0x0) : Use the current default method (Default)
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- HwEq (0x1) : Use Adaptive Hardware Equalization
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- SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
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- Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
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- Disabled (0x4) : Bypass Equalization Phase 3
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**/
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UINT32 DmiGen3EqPh3Method : 3;
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/**
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Offset 28:7 :
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<b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
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- Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
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- <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
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**/
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UINT32 DmiGen3ProgramStaticEq : 1;
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/**
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Offset 28:8 to 28:15 :
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<b>(Test)</b> PEG Enable Control
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- Disabled (0x0) : Disable PEG Port
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- Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it)
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- <b>Auto</b> (0x2) : If an endpoint is present, enable the PEG Port, Disable otherwise (Default)
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**/
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UINT32 Peg0Enable : 2; ///< Enable/Disable PEG 0:1:0 Root Port
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UINT32 Peg1Enable : 2; ///< <b>(Test)</b> Enable/Disable PEG 0:1:1 Root Port
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UINT32 Peg2Enable : 2; ///< <b>(Test)</b> Enable/Disable PEG 0:1:2 Root Port
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UINT32 Peg3Enable : 2; ///< <b>(Test)</b> Enable/Disable PEG 0:6:0 Root Port.
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/**
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Offset 28:16 :
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<b>(Test)</b> PCIe Link Speed Control
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- <b>Auto</b> (0x0) : Maximum possible Link speed (Default)
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- Gen1 (0x1) : Limit Link to Gen1 Speed
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- Gen2 (0x2) : Limit Link to Gen2 Speed
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- Gen3 (0x3) : Limit Link to Gen3 Speed
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**/
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UINT32 Peg0MaxLinkSpeed : 2; ///< PCIe Link Speed Control for PEG 0:1:0 Root Port.
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UINT32 Peg1MaxLinkSpeed : 2; ///< <b>(Test)</b> PCIe Link Speed Control for PEG 0:1:1 Root Port.
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UINT32 Peg2MaxLinkSpeed : 2; ///< <b>(Test)</b> PCIe Link Speed Control for PEG 0:1:2 Root Port.
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UINT32 Peg3MaxLinkSpeed : 2; ///< <b>(Test)</b> PCIe Link Speed Control for PEG 0:6:0 Root Port.
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UINT32 RsvdBits0 : 8; ///< Offset 28:24 :Reserved for future use
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/**
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Offset 32:0 :
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<b>(Test)</b> PCIe Link Width Control
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- <b>Auto</b> (0x0) : Maximum possible Link width (Default)
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- X1 (0x1) : Limit Link to X1 Width
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- X2 (0x2) : Limit Link to X2 Width
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- X4 (0x3) : Limit Link to X4 Width
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- X8 (0x4) : Limit Link to X8 Width
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**/
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UINT32 Peg0MaxLinkWidth : 3; ///< PCIe Link Width Control for PEG 0:1:0 Root Port.
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UINT32 Peg1MaxLinkWidth : 3; ///< <b>(Test)</b> PCIe Link Width Control for PEG 0:1:1 Root Port.
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UINT32 Peg2MaxLinkWidth : 3; ///< <b>(Test)</b> PCIe Link Width Control for PEG 0:1:2 Root Port.
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UINT32 Peg3MaxLinkWidth : 3; ///< <b>(Test)</b> PCIe Link Width Control for PEG 0:6:0 Root Port.
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/**
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Offset 32:12 to 32:15 :
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Power down unused lanes on the PEG Root Port.
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- Disabled (0x0) : No power saving.
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- <b>Auto</b> (0x1) : Bios will power down unused lanes based on the max possible link width
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**/
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UINT32 Peg0PowerDownUnusedLanes : 1; ///< Power down unused lanes on the PEG 0:1:0 Root Port.
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UINT32 Peg1PowerDownUnusedLanes : 1; ///< Power down unused lanes on the PEG 0:1:1 Root Port.
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UINT32 Peg2PowerDownUnusedLanes : 1; ///< Power down unused lanes on the PEG 0:1:2 Root Port.
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UINT32 Peg3PowerDownUnusedLanes : 1; ///< Power down unused lanes on the PEG 0:6:0 Root Port.
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/**
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Offset 32:16 to 32:23 :
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<b>(Test)</b> PCIe Equalization Phase 2 Enable Control
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- Disabled (0x0) : Disable phase 2
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- Enabled (0x1) : Enable phase 2
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- <b>Auto</b> (0x2) : Use the current default method (Default)
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**/
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UINT32 Peg0Gen3EqPh2Enable : 2; ///< Phase2 EQ enable on the PEG 0:1:0 Root Port.
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UINT32 Peg1Gen3EqPh2Enable : 2; ///< <b>(Test)</b> Phase2 EQ enable on the PEG 0:1:1 Root Port.
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UINT32 Peg2Gen3EqPh2Enable : 2; ///< <b>(Test)</b> Phase2 EQ enable on the PEG 0:1:2 Root Port.
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UINT32 Peg3Gen3EqPh2Enable : 2; ///< <b>(Test)</b> Phase2 EQ enable on the PEG 0:6:0 Root Port.
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UINT32 RsvdBits1 : 8; ///< Offset 32:24 :Reserved for future use
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/**
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Offset 36:0 to 36:11 :
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<b>(Test)</b> Select the method for performing Phase3 of Gen3 Equalization.
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- <b>Auto</b> (0x0) : Use the current default method (Default)
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- HwEq (0x1) : Use Adaptive Hardware Equalization
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- SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
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- Static (0x3) : Use the Static EQs provided in PegGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
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- Disabled (0x4) : Bypass Equalization Phase 3
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**/
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UINT32 Peg0Gen3EqPh3Method : 3; ///< Phase3 EQ method on the PEG 0:1:0 Root Port.
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UINT32 Peg1Gen3EqPh3Method : 3; ///< <b>(Test)</b> Phase3 EQ method on the PEG 0:1:1 Root Port.
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UINT32 Peg2Gen3EqPh3Method : 3; ///< <b>(Test)</b> Phase3 EQ method on the PEG 0:1:2 Root Port.
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UINT32 Peg3Gen3EqPh3Method : 3; ///< <b>(Test)</b> Phase3 EQ method on the PEG 0:6:0 Root Port.
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/**
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Offset 36:12 :
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<b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
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- Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
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- <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
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**/
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UINT32 PegGen3ProgramStaticEq : 1;
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/**
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Offset 36:13 :
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<b>(Test)</b> Always Attempt Gen3 Software Equalization
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When enabled, Gen3 Software Equalization will be executed every boot. When disabled, it will be only executed if the CPU
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or EP is changed, otherwise it is skipped and the previous EQ value will be re-used.
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This setting will only have an effect if Software Equalization is enabled and OEM Platform Code implements
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save/restore of the PegDataPtr data (see below). If PegDataPtr is not saved/restored RC forces this to be enabled.
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- <b>Disabled</b> (0x0) : Reuse EQ settings saved/restored from NVRAM whenever possible (Default)
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- Enabled (0x1) : Re-test and generate new EQ values every boot, not recommended
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**/
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UINT32 Gen3SwEqAlwaysAttempt : 1;
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/**
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Offset 36:14 to 36:16 :
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<b>(Test)</b> Select number of TxEq presets to test in the PCIe/DMI Software Equalization Algorithm
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- P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8
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- P0-P9 (0x1) : Test Presets 0-9
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- <b>Auto</b> (0x2) : Use the current default method (Default)
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Auto will test Presets 7, 3, 5, and 8. It is possible for this default to change over time;
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using "Auto" will ensure Reference Code always uses the latest default settings.
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@warning Do not change from the default. Hard to detect issues are likely.
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**/
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UINT32 Gen3SwEqNumberOfPresets : 3;
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/**
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Offset 36:17 to 36:18:
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<b>(Test)</b> Offset 36 Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm
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- Disabled (0x0) : Disable VOC Test
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- Enabled (0x1) : Enable VOC Test
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- <b>Auto</b> (0x2) : Use the current default (Default)
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**/
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UINT32 Gen3SwEqEnableVocTest : 2;
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/**
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Offset 36:19 :
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Select when PCIe ASPM programming will happen in relation to the Oprom
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- <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom. (Default)
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- After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.
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**/
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UINT32 InitPcieAspmAfterOprom : 1;
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/**
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Offset 36:20 :
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<b>(Test)</b> PCIe Rx Compliance Testing Mode
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- <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe Rx Compliance testing (Default)
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- Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing
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**/
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UINT32 PegRxCemTestingMode : 1;
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/**
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Offset 36:21 to 36:24 :
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<b>(Test)</b> PCIe Rx Compliance Loopback Lane
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When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) will be
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used for RxCEMLoopback.
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Default is Lane 0.
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**/
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UINT32 PegRxCemLoopbackLane : 4;
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/**
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Offset 36:25 to 36:28 :
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<b>(Test)</b> Generate PCIe BDAT Margin Table. Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.
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- <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe BDAT margin data generation (Default)
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- PortData (0x1) : Port Data - Generate PCIe BDAT margin data
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**/
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UINT32 PegGenerateBdatMarginTable : 4;
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/**
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Offset 36:29 :
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<b>(Test)</b> PCIe Non-Protocol Awareness for Rx Compliance Testing
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- <b>Disabled</b> (0x0) : Normal Operation - Disable non-protocol awareness (Default)
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- Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing
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**/
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UINT32 PegRxCemNonProtocolAwareness : 1;
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/**
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Offset 36:30 :
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<b>(Test)</b> PCIe Disable Spread Spectrum Clocking. This feature should be TRUE only for compliance testing
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- <b>False</b> (0x0) : Normal Operation - SSC enabled (Default)
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- True (0x1) : Disable SSC - Disable SSC for compliance testing
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**/
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UINT32 PegDisableSpreadSpectrumClocking : 1;
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UINT32 RsvdBits2 : 1;
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UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Offset 40 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
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UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Offset 44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
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UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
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/**
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Offset 52 :
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DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
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has to be specified based upon platform design and must follow the guideline. Default is 0.
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**/
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UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
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UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE]; ///< Offset 54 <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
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UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE]; ///< Offset 70 <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
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UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE]; ///< Offset 86 <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
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/**
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Offset 102:
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PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
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has to be specified based upon platform design and must follow the guideline. Default is 12.
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**/
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UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE];
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/**
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Offset 110:
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<b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 1000.
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@warning Do not change from the default. Hard to detect issues are likely.
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@note An attack on this policy could result in an apparent hang,
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but the system will eventually boot. This variable should be protected.
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**/
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UINT16 Gen3SwEqJitterDwellTime;
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/**
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Offset 112:
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This is a memory data pointer for saved preset search results. The reference code will store
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the Gen3 Preset Search results in the SaPegHob. In order to skip the Gen3
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preset search on boots where the PEG card configuration has not changed since the previous boot,
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platform code can save the contents of the SaPegHob in DXE (When it present and for size reported by Header.HobLength)
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and provide a pointer to a restored copy of that data. Default value is NULL, which results in a full
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preset search every boot.
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@note An attack on this policy could prevent the PCIe display from working until a boot when
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PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable used to save the
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preset search results should be protected in a way that it can only be modified by the
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platform manufacturer.
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**/
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VOID *PegDataPtr;
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/**
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Offset 116:
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<b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 1.
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@warning Do not change from the default. Hard to detect issues are likely.
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**/
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UINT16 Gen3SwEqJitterErrorTarget;
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/**
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Offset 118:
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<b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 10000.
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@warning Do not change from the default. Hard to detect issues are likely.
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@note An attack on this policy could result in an apparent hang,
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but the system will eventually boot. This variable should be protected.
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**/
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UINT16 Gen3SwEqVocDwellTime;
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/**
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Offset 120:
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<b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 2.
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@warning Do not change from the default. Hard to detect issues are likely.
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**/
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UINT16 Gen3SwEqVocErrorTarget;
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/**
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Offset 122:
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PCIe Hot Plug Enable/Disable. It has 2 policies.
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- Disabled (0x0) : No hotplug.
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- Enabled (0x1) : Bios assist hotplug.
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**/
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UINT8 PegRootPortHPE[SA_PEG_MAX_FUN];
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UINT8 DmiDeEmphasis; ///< Offset 125 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
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UINT8 Rsvd0[2]; ///< Offset 126
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/**
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Offset 128:
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This contains the PCIe PERST# GPIO information. This structure is required
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for PCIe Gen3 operation. The reference code will use the information in this structure in
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order to reset PCIe Gen3 devices during equalization, if necessary. Refer to the Platform
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Developer's Guide (PDG) for additional details.
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**/
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PEG_GPIO_DATA PegGpioData;
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/**
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Offset 156
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<b>(Test)</b> PCIe Override RxCTLE. This feature should only be true to disable RxCTLE adaptive behavior for compliance testing
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- <b>False</b> (0x0) : Normal Operation - RxCTLE adaptive behavior enabled (Default)
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- True (0x1) : Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified
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From CFL onwards, modularity is introduced to this setup option so that the RxCTLE adaptive behavior could be controlled at the controller level.
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Making this variable a UINT8 to accomodate the values of all controllers as bit definition
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**/
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UINT8 PegGen3RxCtleOverride;
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UINT8 Reserved1;
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UINT16 Reserved2;
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} PCIE_PEI_PREMEM_CONFIG;
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#pragma pack(pop)
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#endif // _PCIE_PEI_PREMEM_CONFIG_H_
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