/** @file
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Policy definition for PCIe Config Block
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_PEI_CONFIG_H_
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#define _PCIE_PEI_CONFIG_H_
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#include <Library/GpioLib.h>
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#include <SaAccess.h>
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#pragma pack(push, 1)
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#define SA_PCIE_PEI_CONFIG_REVISION 1
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/**
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PCI Express and DMI controller configuration - PostMem\n
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@note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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/**
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Offset 28:0
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<b>(Test)</b>DMI Extended Sync Control
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- <b>Disabled</b> (0x0) : Disable DMI Extended Sync (Default)
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- Enabled (0x1) : Enable DMI Extended Sync
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**/
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UINT32 DmiExtSync : 1;
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/**
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Offset 28:1
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<b>(Test)</b>DMI IOT Control
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- <b>Disabled</b> (0x0) : Disable DMI IOT (Default)
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- Enabled (0x1) : Enable DMI IOT
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**/
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UINT32 DmiIot : 1;
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UINT32 RsvdBits1 : 30; ///< Offset 28:2-31 :Reserved for future use.
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UINT8 DmiAspm; ///< Offset 32 This field is used to describe the ASPM control for DMI: <b>3=PcieAspmL0sL1</b>, 2=PcieAspmL1, 1=PcieAspmL0s, 0=PcieAspmDisabled.
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UINT8 Rsvd1[3]; ///< Offset 33 to 35
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UINT8 PegDeEmphasis[SA_PEG_MAX_FUN]; ///< Offset 36 This field is used to describe the DeEmphasis control for PEG (-6 dB and -3.5 dB are the options)SA_PEG_MAX_FUN = 3 for CFL and SA_PEG_MAX_FUN = 4 for CNL, offsets are adjusted accordingly
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UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///< <b>(Test)</b> Offset 39/40 This field is used to describe the PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B)
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/**
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PCIe Slot Power Capabilities. SlotPowerLimitValue in combination with SlotPowerLimitScale specifies the upper limit on power supplied by slot.
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**/
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UINT8 PegSlotPowerLimitValue[SA_PEG_MAX_FUN]; ///< Offset 42/44 8 bit value
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UINT8 PegSlotPowerLimitScale[SA_PEG_MAX_FUN]; ///< Offset 45/48 2 bit value: <b>00 = 1.0x</b>, 01 = 0.1x, 10 = 0.01x and 11 = 0.001x
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/**
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Offset 48/52
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PCIe Physical Slot Number (13 bit value). Indicates the physical slot number attached to the port.
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**/
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UINT16 PegPhysicalSlotNumber[SA_PEG_MAX_FUN];
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UINT8 Rsvd2[2];
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} PCIE_PEI_CONFIG;
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#pragma pack(pop)
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#endif // _PCIE_PEI_CONFIG_H_
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