/** @file
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Policy definition for Internal Graphics Config Block (PostMem)
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _GRAPHICS_PEI_CONFIG_H_
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#define _GRAPHICS_PEI_CONFIG_H_
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#pragma pack(push, 1)
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#define GRAPHICS_PEI_CONFIG_REVISION 4
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#define DDI_DEVICE_NUMBER 4
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//
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// DDI defines
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//
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typedef enum {
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DdiDisable = 0x00,
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DdiDdcEnable = 0x01,
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DdiTbtLsxEnable = 0x02,
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} DDI_DDC_TBT_VAL;
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typedef enum {
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DdiHpdDisable = 0x00,
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DdiHpdEnable = 0x01,
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} DDI_HPD_VAL;
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typedef enum {
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DdiPortADisabled = 0x00,
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DdiPortAEdp = 0x01,
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DdiPortAMipiDsi = 0x02,
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} DDI_PORTA_SETTINGS;
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/**
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This structure configures the Native GPIOs for DDI port per VBT settings.
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**/
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typedef struct {
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UINT8 DdiPortEdp; /// The setting of eDP port, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortDHpd; /// The HPD setting of DDI Port D, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortFHpd; /// The HPD setting of DDI Port F, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortDDdc; /// The DDC setting of DDI Port D, this settings must match VBT's settings. 0- Disable, <b>1- Enable</b>
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UINT8 DdiPortFDdc; /// The DDC setting of DDI Port F, this settings must match VBT's settings. <b>0- Disable</b>, 1- Enable
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UINT8 Rsvd[3]; ///< Reserved for 4 bytes alignment
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} DDI_CONFIGURATION;
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/**
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This configuration block is to configure IGD related variables used in PostMem PEI.
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If Intel Gfx Device is not supported, all policies can be ignored.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Added SkipS3CdClockInit.
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<b>Revision 3</b>:
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- Added DeltaT12PowerCycleDelay, BltBufferAddress, BltBufferSize.
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<b>Revision 4</b>:
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- Deprecated DeltaT12PowerCycleDelay.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
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UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
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UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
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/**
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Offset 28:3
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CdClock Frequency select\n
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CFL\n
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0 = 337.5 Mhz, 1 = 450 Mhz,\n
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2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n
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**/
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UINT32 CdClock : 3;
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UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
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UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
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UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
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UINT32 DisableTurboGt : 1; ///< Offset 28:9 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
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UINT32 RsvdBits0 : 15; ///< Offser 28:15 :Reserved for future use
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VOID* LogoPtr; ///< Offset 32 Address of Intel Gfx PEIM Logo to be displayed
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UINT32 LogoSize; ///< Offset 36 Intel Gfx PEIM Logo Size
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VOID* GraphicsConfigPtr; ///< Offset 40 Address of the Graphics Configuration Table
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DDI_CONFIGURATION DdiConfiguration; ///< Offset 44 DDI configuration, need to match with VBT settings.
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UINT32 SkipS3CdClockInit : 1; ///< Offset 56 SKip full CD clock initialization being done during S3 resume.<b>0- Disable<\b>, 1- Enable
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UINT32 ReservedBits : 31; ///< Offset 56: 1 : Reserved for future use.
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UINT16 DeltaT12PowerCycleDelay; ///< Offset 60 @deprecated Power Cycle Delay required for eDP as per VESA standard.<b>0 - 0 ms<\b>, 0xFFFF - Auto calculate to max 500 ms
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UINT8 Reserved[2]; ///< Offset 62 Reserved for future use.
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VOID* BltBufferAddress; ///< Offset 64 Address of Blt buffer for PEIM Logo use
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UINT32 BltBufferSize; ///< Offset 68 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
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} GRAPHICS_PEI_CONFIG;
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#pragma pack(pop)
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#endif // _GRAPHICS_PEI_CONFIG_H_
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