/** @file
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This file contains PSF routines for RC usage
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/SataLib.h>
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#include <Library/SaPlatformLib.h>
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#include <Private/Library/PchPsfPrivateLib.h>
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#include <PchLimits.h>
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#include <Register/PchRegsPsf.h>
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#include <Register/PchRegsPcie.h>
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#include "PchPsfPrivateLibInternal.h"
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/**
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Disable device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfDisableDevice (
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IN PSF_PORT PsfPort
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN,
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~0u,
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B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
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);
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}
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/**
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Hide PciCfgSpace of device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfHideDevice (
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IN PSF_PORT PsfPort
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// Read back is needed to enforce the sideband and primary ordering.
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// If there is PCI access right after the PSF hide device, the device might
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// still be accessible since the PSF cycle is not completed yet, and causes
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// the race condition between sideband and primary cycles.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS,
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~0u,
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B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS
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);
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}
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/**
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Unhide PciCfgSpace of device at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfUnhideDevice (
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IN PSF_PORT PsfPort
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS,
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(UINT32) ~(B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS),
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0
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);
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}
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/**
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Disable device BARs at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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@param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,...
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Mask corresponds to 32bit wide BARs
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**/
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VOID
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PsfDisableDeviceBar (
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IN PSF_PORT PsfPort,
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IN UINT32 BarDisMask
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// BAR0-5 supported
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//
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ASSERT (BarDisMask < BIT6);
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN,
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~0u,
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BarDisMask << N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS
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);
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}
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/**
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Enable device BARs at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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@param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,...
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Mask corresponds to 32bit wide BARs
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**/
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VOID
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PsfEnableDeviceBar (
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IN PSF_PORT PsfPort,
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IN UINT32 BarEnMask
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// BAR0-5 supported
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//
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ASSERT (BarEnMask < BIT6);
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN,
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(UINT32)~(BarEnMask << N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS),
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0
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);
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}
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/**
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Disable device IOSpace at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfDisableDeviceIoSpace (
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IN PSF_PORT PsfPort
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN,
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~(UINT32)(B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN),
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0
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);
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}
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/**
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Enable device IOSpace at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfEnableDeviceIoSpace (
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IN PSF_PORT PsfPort
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)
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{
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN,
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~0u,
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B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN
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);
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}
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/**
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Set device BARx address at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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@param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...)
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@param[in] BarValue 32bit BAR value
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**/
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VOID
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PsfSetDeviceBarValue (
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IN PSF_PORT PsfPort,
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IN UINT8 BarNum,
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IN UINT32 BarValue
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)
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{
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ASSERT (BarNum < 6);
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if (PSF_IS_PORT_NULL (PsfPort)) {
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ASSERT (FALSE);
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return;
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}
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//
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// Read back is needed to enforce the sideband and primary ordering.
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//
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PchPcrAndThenOr32WithReadback (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR0 + BarNum * 0x4,
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0,
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BarValue
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);
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}
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/**
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Hide PMC device at PSF level
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**/
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VOID
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PsfHidePmcDevice (
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VOID
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)
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{
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PsfHideDevice (PsfPmcPort ());
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}
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/**
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Set PMC ABASE value in PSF
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@param[in] Address Address for ACPI base address.
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**/
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VOID
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PsfSetPmcAbase (
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IN UINT16 Address
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)
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{
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PSF_PORT PsfPort;
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PsfPort = PsfPmcPort ();
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ASSERT (PchPcrRead32 (PsfPort.PsfPid, PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR4) != 0xFFFFFFFF);
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//
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// Disable IOSpace before changing the address
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//
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PsfDisableDeviceIoSpace (PsfPort);
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//
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// Program ABASE in PSF PMC space BAR4
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//
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PsfSetDeviceBarValue (PsfPort, 4, Address);
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//
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// Enable IOSpace
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//
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PsfEnableDeviceIoSpace (PsfPort);
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}
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/**
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Get PMC ABASE value from PSF
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@retval Address Address for ACPI base.
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**/
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UINT16
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PsfGetPmcAbase (
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VOID
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)
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{
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UINT16 Address;
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PSF_PORT PsfPort;
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PsfPort = PsfPmcPort ();
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//
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// Read ABASE from PSF PMC space BAR4
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//
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Address = PchPcrRead16 (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR4
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);
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ASSERT (Address != 0xFFFF);
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return Address;
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}
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/**
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Get PMC PWRMBASE value from PSF
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@retval Address Address for PWRM base.
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**/
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UINT32
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PsfGetPmcPwrmBase (
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VOID
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)
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{
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UINT32 Address;
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PSF_PORT PsfPort;
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PsfPort = PsfPmcPort ();
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//
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// Read PWRMBASE from PSF PMC space BAR0
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//
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Address = PchPcrRead32 (
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PsfPort.PsfPid,
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PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR0
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);
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ASSERT (Address != 0xFFFFFFFF);
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return Address;
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}
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/**
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Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...)
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@param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)
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@retval PSF SideBand Port ID
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**/
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PCH_SBI_PID
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PsfSbPortId (
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UINT32 PsfId
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)
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{
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UINT32 PsfTableIndex;
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PSF_SEGMENT *PsfTable;
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UINT32 PsfTableSize;
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PsfSegments (&PsfTable, &PsfTableSize);
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for (PsfTableIndex = 0; PsfTableIndex < PsfTableSize; PsfTableIndex++) {
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if (PsfTable[PsfTableIndex].Id == PsfId) {
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return PsfTable[PsfTableIndex].SbPid;
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}
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}
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ASSERT (FALSE);
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return 0;
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}
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/**
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Get PCH Root PSF ID. This is the PSF segment to which OPDMI/DMI is connected.
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@retval PsfId Root PSF ID
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**/
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UINT32
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PsfRootId (
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VOID
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)
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{
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PSF_SEGMENT *PsfTable;
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UINT32 PsfTableSize;
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PsfSegments (&PsfTable, &PsfTableSize);
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return PsfTable[0].Id;
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}
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/**
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Add EOI Target in a given PSF
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@param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)
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@param[in] TargetId EOI Target ID
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**/
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STATIC
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VOID
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PsfAddEoiTarget (
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UINT32 PsfId,
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PSF_PORT_DEST_ID TargetId
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)
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{
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UINT16 EoiTargetBase;
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UINT16 EoiControlBase;
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UINT8 NumOfEnabledTargets;
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UINT8 MaximalNumberOfTargets;
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PCH_SBI_PID PsfSbiPortId;
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UINT32 Data32;
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UINT8 TargetIndex;
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MaximalNumberOfTargets = PsfEoiRegData (PsfId, &EoiTargetBase, &EoiControlBase);
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PsfSbiPortId = PsfSbPortId (PsfId);
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//
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// Get number of enabled agents from PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI register
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//
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Data32 = PchPcrRead32 (PsfSbiPortId, EoiControlBase);
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NumOfEnabledTargets = (UINT8) (Data32 >> N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC);
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//
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// Check if target was not already enabled
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// Targets from a different PSF segment are aggregated into single destination on
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// current PSF segment.
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//
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for (TargetIndex = 0; TargetIndex < NumOfEnabledTargets; TargetIndex++) {
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Data32 = PchPcrRead32 (PsfSbiPortId, EoiTargetBase + TargetIndex * 4);
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//
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// If target already added don't add it again
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//
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if (Data32 == TargetId.RegVal) {
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ASSERT (FALSE);
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return;
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}
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//
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// If target is from different PSF segment than currently being analyzed
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// it is enough that its PsfID is matching
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//
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if ((Data32 & B_PCH_PSFX_PCR_TARGET_PSFID) >> N_PCH_PSFX_PCR_TARGET_PSFID == TargetId.Fields.PsfId) {
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return;
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}
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}
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//
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// Check if next one can be added
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//
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if (NumOfEnabledTargets >= MaximalNumberOfTargets) {
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ASSERT (FALSE);
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return;
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}
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//
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// Add next target
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// Configure Multicast Destination ID register with target device on PSF.
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// Configuration must be done in next available PSF_MC_AGENT_MCAST0_RS0_TGT<x>_EOI register
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// so that other targets are not overridden. <x> is known from the number of multicast agents
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// in Multicast Control Register. Value programmed is based on
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// PsfID, PortGroupID, PortID and ChannelID of the target
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//
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PchPcrWrite32 (PsfSbiPortId, EoiTargetBase + NumOfEnabledTargets * 4, TargetId.RegVal);
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//
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// Enable new target
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// Configure PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI, increase NumMc and set MultCEn
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//
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NumOfEnabledTargets++;
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Data32 = (NumOfEnabledTargets << N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC) | B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN;
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PchPcrWrite32 (PsfSbiPortId, EoiControlBase, Data32);
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}
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/**
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Enable EOI Target
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@param[in] TargetId Target ID
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**/
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STATIC
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VOID
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PsfEnableEoiTarget (
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PSF_PORT_DEST_ID TargetId
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)
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{
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UINT32 RootLevelPsf;
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RootLevelPsf = PsfRootId ();
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//
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// Enable EOI target in root PSF
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//
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PsfAddEoiTarget (RootLevelPsf, TargetId);
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//
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// Enable EOI target on other PSF segment if target
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// is not located on root PSF
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//
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if (TargetId.Fields.PsfId != RootLevelPsf) {
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PsfAddEoiTarget (TargetId.Fields.PsfId, TargetId);
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}
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}
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/**
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This function enables EOI message forwarding in PSF for PCIe ports
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for cases where IOAPIC is present behind this root port.
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@param[in] RpIndex Root port index (0 based)
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@retval Status
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**/
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EFI_STATUS
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PsfConfigurEoiForPciePort (
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IN UINT32 RpIndex
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)
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{
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ASSERT (RpIndex < GetPchMaxPciePortNum ());
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//
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// If there is an IOAPIC discovered behind root port program PSF Multicast registers
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// accordingly to PCH BWG PSF EOI Multicast Configuration
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// Since there is a device behind RootPort to which EOI needs to be forwarded
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// enable multicast (MULTCEN) and increase the number of multicast agents (NUMMC)
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// in Multicast Control Register.
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//
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PsfEnableEoiTarget (PsfPcieDestinationId (RpIndex));
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return EFI_SUCCESS;
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}
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