/** @file
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Pch common library for PCH INIT PEI/DXE/SMM modules
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciSegmentLib.h>
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#include <PchPolicyCommon.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/PchSbiAccessLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/SataLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Register/PchRegsPcie.h>
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extern CONST PCH_PCIE_CONTROLLER_INFO mPchPcieControllerInfo[];
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extern CONST UINT32 mPchPcieControllerInfoSize;
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#define PORT_PLS_TIMEOUT 100 ///< 100 * 10 us = 1ms timeout for USB3 PortSC PLS polling
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/**
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This function returns PID according to PCIe controller index
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@param[in] ControllerIndex PCIe controller index
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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PchGetPcieControllerSbiPid (
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IN UINT32 ControllerIndex
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)
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{
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ASSERT (ControllerIndex < mPchPcieControllerInfoSize);
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return mPchPcieControllerInfo[ControllerIndex].Pid;
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}
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/**
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This function returns PID according to Root Port Number
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@param[in] RpIndex Root Port Index (0-based)
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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GetRpSbiPid (
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IN UINTN RpIndex
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)
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{
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return PchGetPcieControllerSbiPid ((UINT32) (RpIndex / PCH_PCIE_CONTROLLER_PORTS));
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}
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/**
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Calculate root port device number based on physical port index.
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@param[in] RpIndex Root port index (0-based).
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@retval Root port device number.
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**/
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UINT32
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PchGetPcieRpDevice (
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IN UINT32 RpIndex
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)
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{
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UINTN ControllerIndex;
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ControllerIndex = RpIndex / PCH_PCIE_CONTROLLER_PORTS;
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ASSERT (ControllerIndex < mPchPcieControllerInfoSize);
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return mPchPcieControllerInfo[ControllerIndex].DevNum;
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}
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/**
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This function reads Pci Config register via SBI Access
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@param[in] RpIndex Root Port Index (0-based)
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@param[in] Offset Offset of Config register
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@param[out] *Data32 Value of Config register
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@retval EFI_SUCCESS SBI Read successful.
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**/
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EFI_STATUS
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PchSbiRpPciRead32 (
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IN UINT32 RpIndex,
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IN UINT32 Offset,
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OUT UINT32 *Data32
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)
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{
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EFI_STATUS Status;
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UINT32 RpDevice;
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UINT8 Response;
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UINT16 Fid;
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RpDevice = PchGetPcieRpDevice (RpIndex);
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Fid = (UINT16) ((RpDevice << 3) | (RpIndex % 4 ));
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Status = PchSbiExecutionEx (
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GetRpSbiPid (RpIndex),
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Offset,
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PciConfigRead,
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FALSE,
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0xF,
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0,
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Fid,
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Data32,
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&Response
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);
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if (Status != EFI_SUCCESS) {
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DEBUG((DEBUG_ERROR,"Sideband Read Failed of RpIndex %d Offset 0x%x. Device = %d Fid = 0x%x\n",RpIndex, Offset, RpDevice, Fid));
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ASSERT (FALSE);
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}
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return Status;
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}
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/**
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This function And then Or Pci Config register via SBI Access
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@param[in] RpIndex Root Port Index (0-based)
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@param[in] Offset Offset of Config register
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@param[in] Data32And Value of Config register to be And-ed
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@param[in] Data32AOr Value of Config register to be Or-ed
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@retval EFI_SUCCESS SBI Read and Write successful.
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**/
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EFI_STATUS
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PchSbiRpPciAndThenOr32 (
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IN UINT32 RpIndex,
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IN UINT32 Offset,
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IN UINT32 Data32And,
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IN UINT32 Data32Or
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)
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{
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EFI_STATUS Status;
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UINT32 RpDevice;
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UINT32 Data32;
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UINT8 Response;
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UINT16 Fid;
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RpDevice = PchGetPcieRpDevice (RpIndex);
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Status = PchSbiRpPciRead32 (RpIndex, Offset, &Data32);
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if (Status == EFI_SUCCESS) {
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Data32 &= Data32And;
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Data32 |= Data32Or;
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Fid = (UINT16) ((RpDevice << 3) | (RpIndex % 4 ));
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Status = PchSbiExecutionEx (
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GetRpSbiPid (RpIndex),
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Offset,
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PciConfigWrite,
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FALSE,
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0xF,
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0,
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Fid,
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&Data32,
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&Response
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);
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if (Status != EFI_SUCCESS) {
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DEBUG((DEBUG_ERROR,"Sideband Write Failed of RpIndex %d Offset 0x%x. Device = %d Fid = 0x%x\n",RpIndex, Offset, RpDevice, Fid));
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ASSERT (FALSE);
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}
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} else {
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ASSERT (FALSE);
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}
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return Status;
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}
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/**
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Print registers value
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@param[in] PrintMmioBase Mmio base address
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@param[in] PrintSize Number of registers
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@param[in] OffsetFromBase Offset from mmio base address
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@retval None
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**/
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VOID
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PrintRegisters (
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IN UINTN PrintMmioBase,
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IN UINT32 PrintSize,
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IN UINT32 OffsetFromBase
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)
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{
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UINT32 Offset;
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DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F"));
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for (Offset = 0; Offset < PrintSize; Offset++) {
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if ((Offset % 16) == 0) {
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DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFFF0));
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}
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DEBUG ((DEBUG_VERBOSE, "%02X ", MmioRead8 (PrintMmioBase + Offset)));
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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}
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/**
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Print registers value
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@param[in] PrintPciSegmentBase Pci segment base address
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@param[in] PrintSize Number of registers
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@param[in] OffsetFromBase Offset from mmio base address
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@retval None
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**/
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VOID
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PrintPciRegisters (
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IN UINT64 PrintPciSegmentBase,
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IN UINT32 PrintSize,
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IN UINT32 OffsetFromBase
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)
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{
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UINT32 Offset;
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DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F"));
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for (Offset = 0; Offset < PrintSize; Offset++) {
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if ((Offset % 16) == 0) {
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DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFFF0));
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}
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DEBUG ((DEBUG_VERBOSE, "%02X ", PciSegmentRead8 (PrintPciSegmentBase + Offset)));
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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}
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