/** @file
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PCH DMI library.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcrLib.h>
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#include <Private/Library/PchDmiLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Private/Library/PchPsfPrivateLib.h>
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#include <Register/PchRegsPcr.h>
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#include <Register/PchRegsDmi.h>
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#include "PchDmi14.h"
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#include "PchDmi15.h"
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/**
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This function checks if DMI Secured Register Lock (SRL) is set
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@retval SRL state
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**/
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BOOLEAN
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IsPchDmiLocked (
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VOID
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)
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{
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if (IsPchWithPdmi ()) {
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return IsPchDmi15Locked ();
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} else {
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return IsPchDmi14Locked ();
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}
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}
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/**
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Backward DMI library API compatibility
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ACPI base address programming is done in PSF
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@param[in] Address Address for ACPI base.
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@retval EFI_UNSUPPORTED NOT supported programming.
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**/
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EFI_STATUS
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PchDmiSetAcpiBase (
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IN UINT16 Address
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Backward DMI library API compatibility
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PWRMBASE is a standard BAR and doesn't require
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additional DMI base decoding programming
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@param[in] Address Address for PWRM base.
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@retval EFI_UNSUPPORTED NOT supported programming.
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**/
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EFI_STATUS
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PchDmiSetPwrmBase (
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IN UINT32 Address
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Set PCH TCO base address decoding in DMI
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@param[in] Address Address for TCO base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_INVALID_PARAMETER Invalid base address passed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetTcoBase (
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IN UINT16 Address
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)
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{
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI offset 50h[15:5], 1].
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//
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PchPcrWrite16 (
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PID_DMI, R_PCH_DMI_PCR_TCOBASE,
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(Address | BIT1)
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);
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return EFI_SUCCESS;
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}
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/**
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Get PCH TCO base address.
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@retval Address Address of TCO base address.
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**/
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UINT16
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PchDmiGetTcoBase (
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VOID
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)
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{
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//
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// Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
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//
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return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) & B_PCH_DMI_PCR_TCOBASE_TCOBA);
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}
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/**
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Set PCH LPC/eSPI generic IO range decoding in DMI
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@param[in] Address Address for generic IO range base address.
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@param[in] Length Length of generic IO range.
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@param[in] RangeIndex Index of choosen range
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcGenIoRange (
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IN UINT32 Address,
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IN UINT32 Length,
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IN UINT32 RangeIndex
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)
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{
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UINT32 Data32;
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//
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// This cycle decoding is only allowed to set when DMIC.SRL is 0.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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Data32 = (UINT32) (((Length - 1) << 16) & B_LPC_CFG_GENX_DEC_IODRA);
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Data32 |= (UINT32) Address;
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Data32 |= B_LPC_CFG_GENX_DEC_EN;
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//
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// Program LPC Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h.
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//
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PchPcrWrite32 (
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PID_DMI, (UINT16) (R_PCH_DMI_PCR_LPCLGIR1 + RangeIndex * 4),
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Data32
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);
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return EFI_SUCCESS;
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}
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/**
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Set PCH eSPI eSPI CS1# generic IO range decoding in DMI
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@param[in] Address Address for generic IO range base address.
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@param[in] Length Length of generic IO range.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetEspiCs1GenIoRange (
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IN UINT32 Address,
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IN UINT32 Length
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)
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{
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UINT32 Data32;
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//
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// This cycle decoding is only allowed to set when DMIC.SRL is 0.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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Data32 = (UINT32) (((Length - 1) << 16) & B_LPC_CFG_GENX_DEC_IODRA);
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Data32 |= (UINT32) Address;
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Data32 |= B_LPC_CFG_GENX_DEC_EN;
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//
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// Program eSPI Generic IO Range #, PCR[DMI] + 27BCh to the same value programmed in eSPI PCI Offset A4h.
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//
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PchPcrWrite32 (PID_DMI, R_PCH_DMI_PCR_SEGIR, Data32);
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return EFI_SUCCESS;
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}
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/**
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Clear PCH LPC/eSPI generic IO range decoding in DMI
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@param[in] RangeIndex Index of chosen range
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiClearLpcGenIoRange (
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IN UINTN RangeIndex
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)
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{
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//
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// This cycle decoding is only allowed to set when DMIC.SRL is 0.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program LPC Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h.
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//
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PchPcrWrite32 (
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PID_DMI, (UINT16) (R_PCH_DMI_PCR_LPCLGIR1 + RangeIndex * 4),
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0
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);
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return EFI_SUCCESS;
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}
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/**
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Clear PCH eSPI CS1# generic IO range decoding in DMI
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiClearEspiCs1GenIoRange (
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VOID
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)
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{
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//
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// This cycle decoding is only allowed to set when DMIC.SRL is 0.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program LPC Generic IO Range #, PCR[DMI] + 27BCh to the same value programmed in eSPI PCI Offset A4h.
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//
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PchPcrWrite32 (PID_DMI, R_PCH_DMI_PCR_SEGIR, 0);
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return EFI_SUCCESS;
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}
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/**
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Set PCH LPC/eSPI memory range decoding in DMI
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@param[in] Address Address for memory base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcMemRange (
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IN UINT32 Address
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)
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{
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if (IsPchDmiLocked ()) {
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DEBUG ((DEBUG_ERROR, "PchDmiSetLpcMemRange Error. DMI is locked.\n"));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program LPC Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h.
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//
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PchPcrWrite32 (
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PID_DMI, R_PCH_DMI_PCR_LPCGMR,
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(Address | B_LPC_CFG_LGMR_LMRD_EN)
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);
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return EFI_SUCCESS;
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}
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/**
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Set PCH eSPI CS1# memory range decoding in DMI
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@param[in] Address Address for memory base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetEspiCs1MemRange (
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IN UINT32 Address
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)
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{
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if (IsPchDmiLocked ()) {
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DEBUG ((DEBUG_ERROR, "PchLpcMemRange2Set Error. DMI is locked.\n"));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program LPC Memory Range, PCR[DMI] + 27C0h to the same value programmed in eSPI PCI Offset A8h.
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//
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PchPcrWrite32 (
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PID_DMI, R_PCH_DMI_PCR_SEGMR,
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(Address | B_LPC_CFG_LGMR_LMRD_EN)
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);
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return EFI_SUCCESS;
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}
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/**
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Check if Boot BIOS Strap is set for SPI.
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@retval TRUE Boot BIOS Strap set for SPI
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@retval FALSE Boot BIOS Strap set for LPC/eSPI
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**/
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BOOLEAN
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PchDmiIsBootBiosStrapSetForSpi (
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VOID
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)
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{
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//
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// Check General Control and Status (GCS) [10]
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// '0': SPI
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// '1': LPC/eSPI
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//
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return ((PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_GCS) & B_PCH_DMI_PCR_BBS) != B_PCH_DMI_PCR_BBS);
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}
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/**
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Set PCH BIOS range decoding in DMI
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Please check EDS for detail of BiosDecodeEnable bit definition.
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bit 15: F8-FF Enable
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bit 14: F0-F8 Enable
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bit 13: E8-EF Enable
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bit 12: E0-E8 Enable
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bit 11: D8-DF Enable
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bit 10: D0-D7 Enable
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bit 9: C8-CF Enable
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bit 8: C0-C7 Enable
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bit 7: Legacy F Segment Enable
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bit 6: Legacy E Segment Enable
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bit 5: Reserved
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bit 4: Reserved
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bit 3: 70-7F Enable
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bit 2: 60-6F Enable
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bit 1: 50-5F Enable
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bit 0: 40-4F Enable
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@param[in] BiosDecodeEnable Bios decode enable setting.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetBiosDecodeEnable (
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IN UINT16 BiosDecodeEnable
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)
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{
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC or SPI Offset D8h.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCBDE, BiosDecodeEnable);
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return EFI_SUCCESS;
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}
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/**
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Set PCH LPC/eSPI IO decode ranges in DMI
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Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
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Bit 12: FDD range
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Bit 9:8: LPT range
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Bit 6:4: ComB range
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Bit 2:0: ComA range
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@param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcIoDecodeRanges (
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IN UINT16 LpcIoDecodeRanges
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)
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{
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//
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// This cycle decoding is only allowed to set when DMI is not locked.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);
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return EFI_SUCCESS;
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}
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/**
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Set PCH LPC/eSPI IO enable decoding in DMI
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@param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcIoEnable (
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IN UINT16 LpcIoEnableDecoding
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)
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{
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//
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// This cycle decoding is only allowed to set when DMI is not locked.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);
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return EFI_SUCCESS;
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}
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/**
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Set PCH IO port 80h cycle decoding to PCIE root port in DMI
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@param[in] RpNumber PCIE root port physical number.
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@retval EFI_SUCCESS Successfully completed.
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**/
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EFI_STATUS
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PchDmiSetIoPort80Decode (
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IN UINTN RpNumber
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)
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{
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UINT16 DmiRpDestinationId;
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PSF_PORT_DEST_ID PsfRpDestinationId;
|
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if (IsPchDmiLocked ()) {
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DEBUG ((DEBUG_ERROR, "PchIoPort80DecodeSet Error. DMI is locked.\n"));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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///
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/// IO port 80h is typically used by decoder/LED hardware for debug purposes.
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/// By default PCH will forward IO port 80h cycles to LPC bus. The Reserved Page Route (RPR) bit
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/// of General Control and Status register, located at PCR[DMI] + 274Ch[11] , allows software to
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/// re-direct IO port 80h cycles to PCIe bus so that a target (for example, a debug card) on
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/// PCIe bus can receive and claim these cycles.
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/// The "RPR Destination ID", PCR[DMI] + 274Ch[31:16] need to be set accordingly to point
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/// to the root port that decode this range. Reading from Port 80h may not return valid values
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/// if the POST-card itself do not shadow the writes. Unlike LPC, PCIe does not shadow the Port 80 writes.
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///
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PsfRpDestinationId = PsfPcieDestinationId ((UINT32)RpNumber);
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|
DmiRpDestinationId = (UINT16)((0x2 << 12) |
|
(PsfRpDestinationId.Fields.PsfId << 8) |
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(PsfRpDestinationId.Fields.PortGroupId << 7) |
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(PsfRpDestinationId.Fields.PortId << 3) |
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PsfRpDestinationId.Fields.ChannelId);
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//
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// Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_GCS + 2, DmiRpDestinationId);
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//
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// Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'.
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// Use byte write on GCS+1 and leave the BILD bit which is RWO.
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//
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PchPcrAndThenOr8 (PID_DMI, R_PCH_DMI_PCR_GCS + 1, 0xFF, (B_PCH_DMI_PCR_RPR >> 8));
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return EFI_SUCCESS;
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}
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/**
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Set DMI thermal throttling to recommended configuration.
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It's intended only for P-DMI.
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**/
|
VOID
|
PchDmiSetRecommendedThermalThrottling (
|
VOID
|
)
|
{
|
if (IsPchWithPdmi ()) {
|
PchDmi15SetRecommendedThermalThrottling ();
|
}
|
}
|
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/**
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Set DMI thermal throttling to custom configuration.
|
This function will configure Thermal Sensor 0/1/2/3 TargetWidth and set
|
DMI Thermal Sensor Autonomous Width Enable.
|
It's intended only for P-DMI.
|
|
@param[in] DmiThermalThrottling DMI Thermal Throttling structure.
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**/
|
VOID
|
PchDmiSetCustomThermalThrottling (
|
IN DMI_THERMAL_THROTTLING DmiThermalThrottling
|
)
|
{
|
if (IsPchWithPdmi ()) {
|
PchDmi15SetCustomThermalThrottling (DmiThermalThrottling);
|
}
|
}
|
|
/**
|
Determines where to send the reserved page registers
|
Accesses to the I/O ranges 80h - 8Fh will be forwarded to PCIe Root Port
|
with the destination ID specified in GCS.RPRDID using DMI source decode.
|
**/
|
VOID
|
PchDmiSetReservedPageRegToPcieRootPort (
|
VOID
|
)
|
{
|
PchPcrAndThenOr8 (
|
PID_DMI, R_PCH_DMI_PCR_GCS + 1,
|
(UINT8) ~0,
|
(UINT8) (B_PCH_DMI_PCR_RPR >> 8)
|
);
|
}
|
|
/**
|
Determines where to send the reserved page registers
|
DMI will not perform source decode on the I/O ranges 80h - 8Fh. The cycles hitting these ranges will
|
end up in P2SB which will then forward the cycle to LPC or eSPI through IOSF Sideband.
|
**/
|
VOID
|
PchDmiSetReservedPageRegToLpc (
|
VOID
|
)
|
{
|
PchPcrAndThenOr8 (
|
PID_DMI, R_PCH_DMI_PCR_GCS + 1,
|
(UINT8) (~(B_PCH_DMI_PCR_RPR >> 8)),
|
0
|
);
|
}
|
|
/**
|
uCode Patch Region Enable (UPRE). Enables memory access targeting the uCode patch region (0xFEF00000 to 0xFEFFFFFF)
|
to be forwarded to SPI Flash. This can only be set if the boot flash is on SPI.
|
**/
|
VOID
|
PchDmiEnableUCodePatchRegion (
|
VOID
|
)
|
{
|
///
|
/// Setup "uCode Patch Region Enable", PCR [DMI] + 2748h[0] to '0b'
|
///
|
PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI_PCR_UCPR, (UINT32) ~B_PCH_DMI_PCR_UCPR_UPRE, 0);
|
}
|
|
