/** @file
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PCH SPI PEI Library implements the SPI Host Controller Compatibility Interface.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Ppi/Spi.h>
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#include <Private/Library/PchSpiCommonLib.h>
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#include <PchReservedResources.h>
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#include <IndustryStandard/Pci30.h>
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#include <Register/PchRegs.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchRegsSpi.h>
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typedef struct {
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EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
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SPI_INSTANCE SpiInstance;
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} PEI_SPI_INSTANCE;
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/**
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PCI Enumeratuion is not done till later in DXE
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Initlialize SPI BAR0 to a default value till enumeration is done
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also enable memory space decoding for SPI
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**/
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VOID
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InitSpiBar0 (
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VOID
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)
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{
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UINT64 PchSpiBase;
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PchSpiBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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PciSegmentAnd8 (PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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PciSegmentWrite32 (PchSpiBase + R_SPI_CFG_BAR0, PCH_SPI_BASE_ADDRESS);
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PciSegmentOr8 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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}
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/**
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This function Initial SPI services
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@retval EFI_STATUS Results of the installation of the SPI services
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**/
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EFI_STATUS
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EFIAPI
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SpiServiceInit (
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VOID
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)
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{
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EFI_STATUS Status;
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PEI_SPI_INSTANCE *PeiSpiInstance;
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SPI_INSTANCE *SpiInstance;
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PCH_SPI_PPI *SpiPpi;
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Status = PeiServicesLocatePpi (
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&gPchSpiPpiGuid,
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0,
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NULL,
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(VOID **)&SpiPpi
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);
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if (Status != EFI_SUCCESS) {
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DEBUG ((DEBUG_INFO, "SpiServiceInit() Start\n"));
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//
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// PCI Enumeratuion is not done till later in DXE
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// Initlialize SPI BAR0 to a default value till enumeration is done
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// also enable memory space decoding for SPI
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//
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InitSpiBar0 ();
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PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE));
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if (NULL == PeiSpiInstance) {
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return EFI_OUT_OF_RESOURCES;
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}
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SpiInstance = &(PeiSpiInstance->SpiInstance);
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SpiProtocolConstructor (SpiInstance);
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PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
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PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid;
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PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol);
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///
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/// Install the SPI PPI
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///
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DEBUG ((DEBUG_INFO, "SPI PPI Installed\n"));
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Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor);
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ASSERT_EFI_ERROR (Status);
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DEBUG ((DEBUG_INFO, "SpiServiceInit() End\n"));
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}
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else {
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DEBUG ((DEBUG_INFO, "SPI PPI already installed\n"));
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}
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return Status;
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}
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/**
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Acquire pch spi mmio address.
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@param[in] SpiInstance Pointer to SpiInstance to initialize
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@retval PchSpiBar0 return SPI MMIO address
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**/
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UINTN
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AcquireSpiBar0 (
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IN SPI_INSTANCE *SpiInstance
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)
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{
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return PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
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}
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/**
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Release pch spi mmio address. Do nothing.
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@param[in] SpiInstance Pointer to SpiInstance to initialize
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@retval None
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**/
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VOID
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ReleaseSpiBar0 (
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IN SPI_INSTANCE *SpiInstance
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)
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{
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}
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/**
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This function is a hook for Spi to disable BIOS Write Protect
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@retval EFI_SUCCESS The protocol instance was properly initialized
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@retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
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**/
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EFI_STATUS
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EFIAPI
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DisableBiosWriteProtect (
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VOID
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)
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{
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UINT64 SpiBaseAddress;
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SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS) != 0) {
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return EFI_ACCESS_DENIED;
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}
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///
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/// Enable the access to the BIOS space for both read and write cycles
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///
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PciSegmentOr8 (
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SpiBaseAddress + R_SPI_CFG_BC,
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B_SPI_CFG_BC_WPD
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);
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return EFI_SUCCESS;
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}
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/**
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This function is a hook for Spi to enable BIOS Write Protect
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**/
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VOID
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EFIAPI
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EnableBiosWriteProtect (
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VOID
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)
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{
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UINT64 SpiBaseAddress;
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SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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///
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/// Disable the access to the BIOS space for write cycles
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///
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PciSegmentAnd8 (
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SpiBaseAddress + R_SPI_CFG_BC,
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(UINT8) (~B_SPI_CFG_BC_WPD)
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);
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}
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/**
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Check if it's granted to do flash write.
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@retval TRUE It's secure to do flash write.
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@retval FALSE It's not secure to do flash write.
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**/
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BOOLEAN
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IsSpiFlashWriteGranted (
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VOID
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)
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{
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return TRUE;
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}
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