/** @file
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This file is PeiPchPolicy library.
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Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyLibrary.h"
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#include <Library/PchPcieRpLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <Register/PchRegsLpcCnl.h>
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#include <Library/ConfigBlockLib.h>
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/**
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mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped to IRQy).
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This information is used by systems which choose to use legacy PIC
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interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this table
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will be programmed into ITSS.PxRC registers.
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] = {
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11, // PARC: PIRQA -> IRQ11
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10, // PBRC: PIRQB -> IRQ10
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11, // PCRC: PIRQC -> IRQ11
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11, // PDRC: PIRQD -> IRQ11
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11, // PERC: PIRQE -> IRQ11
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11, // PFRC: PIRQF -> IRQ11
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11, // PGRC: PIRQG -> IRQ11
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11 // PHRC: PIRQH -> IRQ11
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};
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadPchGeneralConfigDefault (
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IN VOID *ConfigBlockPointer
|
)
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{
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PCH_GENERAL_CONFIG *PchGeneralConfig;
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PchGeneralConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Name = %g\n", &PchGeneralConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PchGeneralConfig->Header.GuidHob.Header.HobLength));
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/********************************
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PCH general configuration
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********************************/
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadPcieRpConfigDefault (
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IN VOID *ConfigBlockPointer
|
)
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{
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UINTN Index;
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PCH_PCIE_CONFIG *PcieRpConfig;
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PcieRpConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Name = %g\n", &PcieRpConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PcieRpConfig->Header.GuidHob.Header.HobLength));
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/********************************
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PCI Express related settings
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********************************/
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PcieRpConfig->RpFunctionSwap = TRUE;
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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PcieRpConfig->RootPort[Index].Aspm = PchPcieAspmAutoConfig;
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PcieRpConfig->RootPort[Index].PmSci = TRUE;
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PcieRpConfig->RootPort[Index].AcsEnabled = TRUE;
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PcieRpConfig->RootPort[Index].PtmEnabled = TRUE;
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PcieRpConfig->RootPort[Index].DpcEnabled = TRUE;
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PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled = TRUE;
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PcieRpConfig->RootPort[Index].MaxPayload = PchPcieMaxPayload256;
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PcieRpConfig->RootPort[Index].SlotImplemented = TRUE;
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PcieRpConfig->RootPort[Index].PhysicalSlotNumber = (UINT8) Index;
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PcieRpConfig->RootPort[Index].L1Substates = PchPcieL1SubstatesL1_1_2;
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PcieRpConfig->RootPort[Index].EnableCpm = TRUE;
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PcieRpConfig->RootPort[Index].Gen3EqPh3Method = PchPcieEqHardware;
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//
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// PCIe LTR Configuration.
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//
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PcieRpConfig->RootPort[Index].LtrEnable = TRUE;
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PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency = 0x1003;
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PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency = 0x1003;
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PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode = 2;
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PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier = 2;
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PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue = 60;
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PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode = 2;
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PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier = 2;
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PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue = 60;
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PcieRpConfig->RootPort[Index].Uptp = 5;
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PcieRpConfig->RootPort[Index].Dptp = 7;
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PcieRpConfig->EqPh3LaneParam[Index].Cm = 6;
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PcieRpConfig->EqPh3LaneParam[Index].Cp = 2;
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}
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PcieRpConfig->SwEqCoeffList[0].Cm = 4;
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PcieRpConfig->SwEqCoeffList[0].Cp = 8;
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PcieRpConfig->SwEqCoeffList[1].Cm = 6;
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PcieRpConfig->SwEqCoeffList[1].Cp = 2;
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PcieRpConfig->SwEqCoeffList[2].Cm = 8;
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PcieRpConfig->SwEqCoeffList[2].Cp = 6;
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PcieRpConfig->SwEqCoeffList[3].Cm = 10;
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PcieRpConfig->SwEqCoeffList[3].Cp = 8;
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PcieRpConfig->SwEqCoeffList[4].Cm = 12;
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PcieRpConfig->SwEqCoeffList[4].Cp = 2;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadSataConfigDefault (
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IN VOID *ConfigBlockPointer
|
)
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{
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UINTN PortIndex;
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UINTN Index;
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UINT32 SataCtrlIndex;
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PCH_SATA_CONFIG *SataConfig;
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SataConfig = (PCH_SATA_CONFIG *)ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Name = %g\n", &SataConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SataConfig->Header.GuidHob.Header.HobLength));
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for (SataCtrlIndex = 0; SataCtrlIndex < GetPchMaxSataControllerNum (); SataCtrlIndex++, SataConfig++) {
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/********************************
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SATA related settings
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********************************/
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SataConfig->Enable = TRUE;
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SataConfig->SalpSupport = TRUE;
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SataConfig->SataMode = PchSataModeAhci;
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for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (SataCtrlIndex); PortIndex++) {
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SataConfig->PortSettings[PortIndex].Enable = TRUE;
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SataConfig->PortSettings[PortIndex].DmVal = 15;
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SataConfig->PortSettings[PortIndex].DitoVal = 625;
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}
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SataConfig->Rst.Raid0 = TRUE;
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SataConfig->Rst.Raid1 = TRUE;
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SataConfig->Rst.Raid10 = TRUE;
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SataConfig->Rst.Raid5 = TRUE;
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SataConfig->Rst.Irrt = TRUE;
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SataConfig->Rst.OromUiBanner = TRUE;
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SataConfig->Rst.OromUiDelay = PchSataOromDelay2sec;
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SataConfig->Rst.HddUnlock = TRUE;
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SataConfig->Rst.LedLocate = TRUE;
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SataConfig->Rst.IrrtOnly = TRUE;
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SataConfig->Rst.SmartStorage = TRUE;
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SataConfig->Rst.OptaneMemory = TRUE;
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SataConfig->Rst.CpuAttachedStorage = TRUE;
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay = 100;
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}
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SataConfig->PwrOptEnable = TRUE;
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SataConfig->ThermalThrottling.SuggestedSetting = TRUE;
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}
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}
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/**
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Get Sata Config Policy
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@param[in] SiPolicy The RC Policy PPI instance
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@param[in] SataCtrlIndex SATA controller index
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@retval SataConfig Pointer to Sata Config Policy
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**/
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PCH_SATA_CONFIG *
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GetPchSataConfig (
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IN SI_POLICY_PPI *SiPolicy,
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IN UINT32 SataCtrlIndex
|
)
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{
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PCH_SATA_CONFIG *SataConfig;
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EFI_STATUS Status;
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ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ());
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
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ASSERT_EFI_ERROR (Status);
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SataConfig += SataCtrlIndex;
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return SataConfig;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadIoApicConfigDefault (
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IN VOID *ConfigBlockPointer
|
)
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{
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PCH_IOAPIC_CONFIG *IoApicConfig;
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IoApicConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Name = %g\n", &IoApicConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Header.HobLength = 0x%x\n", IoApicConfig->Header.GuidHob.Header.HobLength));
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/********************************
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Io Apic configuration
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********************************/
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IoApicConfig->IoApicId = 0x02;
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IoApicConfig->IoApicEntry24_119 = TRUE;
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IoApicConfig->Enable8254ClockGating = TRUE;
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IoApicConfig->Enable8254ClockGatingOnS3 = TRUE;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
|
LoadDmiConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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PCH_DMI_CONFIG *DmiConfig;
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DmiConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Name = %g\n", &DmiConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", DmiConfig->Header.GuidHob.Header.HobLength));
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/********************************
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DMI related settings
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********************************/
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DmiConfig->DmiAspmCtrl = PchPcieAspmAutoConfig;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadFlashProtectionConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
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FlashProtectionConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Name = %g\n", &FlashProtectionConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Header.HobLength = 0x%x\n", FlashProtectionConfig->Header.GuidHob.Header.HobLength));
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
|
LoadHdAudioConfigDefault (
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IN VOID *ConfigBlockPointer
|
)
|
{
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PCH_HDAUDIO_CONFIG *HdAudioConfig;
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HdAudioConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "HdAudioConfig->Header.GuidHob.Name = %g\n", &HdAudioConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "HdAudioConfig->Header.GuidHob.Header.HobLength = 0x%x\n", HdAudioConfig->Header.GuidHob.Header.HobLength));
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/********************************
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HD-Audio configuration
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********************************/
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HdAudioConfig->DspEnable = TRUE;
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HdAudioConfig->HdAudioLinkFrequency = PchHdaLinkFreq24MHz;
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HdAudioConfig->IDispLinkFrequency = PchHdaLinkFreq96MHz;
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HdAudioConfig->IDispLinkTmode = PchHdaIDispMode2T;
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HdAudioConfig->ResetWaitTimer = 600; // Must be at least 521us (25 frames)
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HdAudioConfig->AudioLinkHda = TRUE;
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HdAudioConfig->AudioLinkDmic0 = TRUE;
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HdAudioConfig->AudioLinkDmic1 = TRUE;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadInterruptConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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PCH_INTERRUPT_CONFIG *InterruptConfig;
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InterruptConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Name = %g\n", &InterruptConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Header.HobLength = 0x%x\n", InterruptConfig->Header.GuidHob.Header.HobLength));
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LoadDeviceInterruptConfig (InterruptConfig);
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ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <= PCH_MAX_PXRC_CONFIG);
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CopyMem (
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InterruptConfig->PxRcConfig,
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mPxRcConfig,
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sizeof (mPxRcConfig)
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);
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InterruptConfig->GpioIrqRoute = 14;
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InterruptConfig->SciIrqSelect = 9;
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InterruptConfig->TcoIrqSelect = 9;
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadIshConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_ISH_CONFIG *IshConfig;
|
IshConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Name = %g\n", &IshConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Header.HobLength = 0x%x\n", IshConfig->Header.GuidHob.Header.HobLength));
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}
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|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadLanConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_LAN_CONFIG *LanConfig;
|
|
LanConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name = %g\n", &LanConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength = 0x%x\n", LanConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Lan configuration
|
********************************/
|
LanConfig->Enable = TRUE;
|
LanConfig->LtrEnable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadLockDownConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_LOCK_DOWN_CONFIG *LockDownConfig;
|
LockDownConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Name = %g\n", &LockDownConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Header.HobLength = 0x%x\n", LockDownConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Lockdown configuration
|
********************************/
|
LockDownConfig->GlobalSmi = TRUE;
|
LockDownConfig->BiosInterface = TRUE;
|
LockDownConfig->RtcMemoryLock = TRUE;
|
LockDownConfig->BiosLock = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadP2sbConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_P2SB_CONFIG *P2sbConfig;
|
P2sbConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Name = %g\n", &P2sbConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Header.HobLength = 0x%x\n", P2sbConfig->Header.GuidHob.Header.HobLength));
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadPmConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_PM_CONFIG *PmConfig;
|
PmConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Name = %g\n", &PmConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PmConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
MiscPm Configuration
|
********************************/
|
PmConfig->MeWakeSts = TRUE;
|
PmConfig->WolOvrWkSts = TRUE;
|
|
PmConfig->WakeConfig.WolEnableOverride = TRUE;
|
PmConfig->WakeConfig.LanWakeFromDeepSx = TRUE;
|
|
PmConfig->PchSlpS3MinAssert = PchSlpS350ms;
|
PmConfig->PchSlpS4MinAssert = PchSlpS41s;
|
PmConfig->PchSlpSusMinAssert = PchSlpSus4s;
|
PmConfig->PchSlpAMinAssert = PchSlpA2s;
|
|
PmConfig->SlpLanLowDc = TRUE;
|
PmConfig->PciePllSsc = 0xFF;
|
PmConfig->LpcClockRun = TRUE;
|
PmConfig->SlpS0Enable = TRUE;
|
PmConfig->CpuC10GatePinEnable = TRUE;
|
if (IsWhlCpu () && (GetCpuStepping () == EnumCflV0)) {
|
PmConfig->SlpS0WithGbeSupport = FALSE;
|
} else {
|
PmConfig->SlpS0WithGbeSupport = TRUE;
|
}
|
|
if (IsPchLp ()) {
|
PmConfig->ModPhySusPgEnable = TRUE;
|
}
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadScsConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_SCS_CONFIG *ScsConfig;
|
ScsConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Name = %g\n", &ScsConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Header.HobLength = 0x%x\n", ScsConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
SCS Configuration
|
********************************/
|
ScsConfig->ScsEmmcEnabled = IsPchLp () ? TRUE : FALSE; // eMMC present on PCH-LP only
|
ScsConfig->ScsEmmcHs400DriverStrength = DriverStrength40Ohm;
|
//Enable Sd Card controller for Non-Desktop sku platforms
|
if (GetCpuSku () != EnumCpuTrad) {
|
ScsConfig->ScsSdcardEnabled = TRUE;
|
}
|
ScsConfig->SdCardPowerEnableActiveHigh = TRUE;
|
ScsConfig->ScsUfsEnabled = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadSerialIoConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
UINTN Index;
|
PCH_SERIAL_IO_CONFIG *SerialIoConfig;
|
SerialIoConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Name = %g\n", &SerialIoConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SerialIoConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
SerialIo Configuration
|
********************************/
|
for (Index = 0; Index < GetPchMaxSerialIoControllersNum (); Index++) {
|
SerialIoConfig->DevMode[Index] = PchSerialIoPci;
|
}
|
SerialIoConfig->DebugUartNumber = PcdGet8 (PcdSerialIoUartNumber);
|
}
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadSerialIrqConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
|
SerialIrqConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Name = %g\n", &SerialIrqConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SerialIrqConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Serial IRQ Configuration
|
********************************/
|
SerialIrqConfig->SirqEnable = TRUE;
|
SerialIrqConfig->SirqMode = PchQuietMode;
|
SerialIrqConfig->StartFramePulse = PchSfpw4Clk;
|
}
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadThermalConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_THERMAL_CONFIG *ThermalConfig;
|
ThermalConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Name = %g\n", &ThermalConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Header.HobLength = 0x%x\n", ThermalConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Thermal configuration.
|
********************************/
|
ThermalConfig->TsmicLock = TRUE;
|
ThermalConfig->PchHotLevel = 0x154;
|
ThermalConfig->TTLevels.SuggestedSetting = TRUE;
|
ThermalConfig->TTLevels.PchCrossThrottling = TRUE;
|
ThermalConfig->DmiHaAWC.SuggestedSetting = TRUE;
|
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
|
ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadUsbConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
UINTN PortIndex;
|
USB_CONFIG *UsbConfig;
|
UsbConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Name = %g\n", &UsbConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Header.HobLength = 0x%x\n", UsbConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
USB related configuration
|
********************************/
|
for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) {
|
UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
|
}
|
|
for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
|
UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
|
}
|
|
//
|
// BIOS should program PDO in PEI phase by default
|
//
|
UsbConfig->PdoProgramming = TRUE;
|
|
//
|
// Default values of USB2 AFE settings.
|
//
|
UsbConfig->Usb2PhySusPgEnable = TRUE;
|
for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) {
|
UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = 3;
|
UsbConfig->PortUsb20[PortIndex].Afe.Txiset = 2;
|
UsbConfig->PortUsb20[PortIndex].Afe.Predeemp = 1;
|
UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit = 1;
|
}
|
|
for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
|
UsbConfig->PortUsb30HsioRx[PortIndex].HsioOlfpsCfgPullUpDwnRes = 3;
|
}
|
|
UsbConfig->XhciOcLock = TRUE;
|
|
//
|
// xDCI configuration
|
//
|
UsbConfig->XdciConfig.Enable = FALSE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadEspiConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_ESPI_CONFIG *EspiConfig;
|
EspiConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Name = %g\n", &EspiConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", EspiConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Espi configuration.
|
********************************/
|
EspiConfig->BmeMasterSlaveEnabled = TRUE;
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadCnviConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_CNVI_CONFIG *CnviConfig;
|
CnviConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "CnviConfig->Header.GuidHob.Name = %g\n", &CnviConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "CnviConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CnviConfig->Header.GuidHob.Header.HobLength));
|
|
/********************************
|
Cnvi configuration.
|
********************************/
|
CnviConfig->Mode = CnviModeAuto; // Automatic detection
|
}
|
|
/**
|
Load Config block default
|
|
@param[in] ConfigBlockPointer Pointer to config block
|
**/
|
VOID
|
LoadHsioConfigDefault (
|
IN VOID *ConfigBlockPointer
|
)
|
{
|
PCH_HSIO_CONFIG *HsioConfig;
|
HsioConfig = ConfigBlockPointer;
|
|
DEBUG ((DEBUG_INFO, "HsioConfig->Header.GuidHob.Name = %g\n", &HsioConfig->Header.GuidHob.Name));
|
DEBUG ((DEBUG_INFO, "HsioConfig->Header.GuidHob.Header.HobLength = 0x%x\n", HsioConfig->Header.GuidHob.Header.HobLength));
|
}
|
|
GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mPchIpBlocks [] = {
|
{&gPchGeneralConfigGuid, sizeof (PCH_GENERAL_CONFIG), PCH_GENERAL_CONFIG_REVISION, LoadPchGeneralConfigDefault},
|
{&gPcieRpConfigGuid, sizeof (PCH_PCIE_CONFIG), PCIE_RP_CONFIG_REVISION, LoadPcieRpConfigDefault},
|
{&gSataConfigGuid, sizeof (PCH_SATA_CONFIG), SATA_CONFIG_REVISION, LoadSataConfigDefault},
|
{&gIoApicConfigGuid, sizeof (PCH_IOAPIC_CONFIG), IOAPIC_CONFIG_REVISION, LoadIoApicConfigDefault},
|
{&gDmiConfigGuid, sizeof (PCH_DMI_CONFIG), DMI_CONFIG_REVISION, LoadDmiConfigDefault},
|
{&gFlashProtectionConfigGuid, sizeof (PCH_FLASH_PROTECTION_CONFIG), FLASH_PROTECTION_CONFIG_REVISION, LoadFlashProtectionConfigDefault},
|
{&gHdAudioConfigGuid, sizeof (PCH_HDAUDIO_CONFIG), HDAUDIO_CONFIG_REVISION, LoadHdAudioConfigDefault},
|
{&gInterruptConfigGuid, sizeof (PCH_INTERRUPT_CONFIG), INTERRUPT_CONFIG_REVISION, LoadInterruptConfigDefault},
|
{&gIshConfigGuid, sizeof (PCH_ISH_CONFIG), ISH_CONFIG_REVISION, LoadIshConfigDefault},
|
{&gLanConfigGuid, sizeof (PCH_LAN_CONFIG), LAN_CONFIG_REVISION, LoadLanConfigDefault},
|
{&gLockDownConfigGuid, sizeof (PCH_LOCK_DOWN_CONFIG), LOCK_DOWN_CONFIG_REVISION, LoadLockDownConfigDefault},
|
{&gP2sbConfigGuid, sizeof (PCH_P2SB_CONFIG), P2SB_CONFIG_REVISION, LoadP2sbConfigDefault},
|
{&gPmConfigGuid, sizeof (PCH_PM_CONFIG), PM_CONFIG_REVISION, LoadPmConfigDefault},
|
{&gScsConfigGuid, sizeof (PCH_SCS_CONFIG), SCS_CONFIG_REVISION, LoadScsConfigDefault},
|
{&gSerialIoConfigGuid, sizeof (PCH_SERIAL_IO_CONFIG), SERIAL_IO_CONFIG_REVISION, LoadSerialIoConfigDefault},
|
{&gSerialIrqConfigGuid, sizeof (PCH_LPC_SIRQ_CONFIG), SERIAL_IRQ_CONFIG_REVISION, LoadSerialIrqConfigDefault},
|
{&gThermalConfigGuid, sizeof (PCH_THERMAL_CONFIG), THERMAL_CONFIG_REVISION, LoadThermalConfigDefault},
|
{&gUsbConfigGuid, sizeof (USB_CONFIG), USB_CONFIG_REVISION, LoadUsbConfigDefault},
|
{&gEspiConfigGuid, sizeof (PCH_ESPI_CONFIG), ESPI_CONFIG_REVISION, LoadEspiConfigDefault},
|
{&gCnviConfigGuid, sizeof (PCH_CNVI_CONFIG), CNVI_CONFIG_REVISION, LoadCnviConfigDefault},
|
{&gHsioConfigGuid, sizeof (PCH_HSIO_CONFIG), HSIO_CONFIG_REVISION, LoadHsioConfigDefault},
|
};
|
|
/**
|
Get PCH config block table total size.
|
|
@retval Size of PCH config block table
|
**/
|
UINT16
|
EFIAPI
|
PchGetConfigBlockTotalSize (
|
VOID
|
)
|
{
|
return GetComponentConfigBlockTotalSize (&mPchIpBlocks[0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
|
}
|
|
/**
|
PchAddConfigBlocks add all PCH config blocks.
|
|
@param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
|
|
@retval EFI_SUCCESS The policy default is initialized.
|
@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
|
**/
|
EFI_STATUS
|
EFIAPI
|
PchAddConfigBlocks (
|
IN VOID *ConfigBlockTableAddress
|
)
|
{
|
DEBUG ((DEBUG_INFO, "PCH AddConfigBlocks\n"));
|
|
return AddComponentConfigBlocks (ConfigBlockTableAddress, &mPchIpBlocks[0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
|
}
|
