/** @file
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PCH SBI access library.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchSbiAccessLib.h>
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#include <Register/PchRegs.h>
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#include <Register/PchRegsP2sb.h>
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/**
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Execute PCH SBI message
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Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
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It will clash with POST time SBI programming when SMI happen.
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Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
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to prevent from racing condition.
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This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
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needed, it's better to unhide the P2SB before calling and hide it back after done.
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When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
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SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
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when needed.
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@param[in] Pid Port ID of the SBI message
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@param[in] Offset Offset of the SBI message
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@param[in] Opcode Opcode
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@param[in] Posted Posted message
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@param[in, out] Data32 Read/Write data
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@param[out] Response Response
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_DEVICE_ERROR Transaction fail
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@retval EFI_INVALID_PARAMETER Invalid parameter
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@retval EFI_TIMEOUT Timeout while waiting for response
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**/
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EFI_STATUS
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EFIAPI
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PchSbiExecution (
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IN PCH_SBI_PID Pid,
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IN UINT64 Offset,
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IN PCH_SBI_OPCODE Opcode,
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IN BOOLEAN Posted,
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IN OUT UINT32 *Data32,
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OUT UINT8 *Response
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)
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{
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//
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// Check address valid
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//
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if (((UINT32) Offset & 0x3) != 0) {
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//
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// Warning message for the address not DWORD alignment.
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//
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DEBUG ((DEBUG_INFO, "PchSbiExecution: Address is not DWORD aligned.\n"));
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}
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return PchSbiExecutionEx ( Pid,
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Offset,
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Opcode,
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Posted,
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0x000F,
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0x0000,
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0x0000,
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Data32,
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Response
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);
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}
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/**
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Full function for executing PCH SBI message
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Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
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It will clash with POST time SBI programming when SMI happen.
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Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
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to prevent from racing condition.
|
This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
|
needed, it's better to unhide the P2SB before calling and hide it back after done.
|
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When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
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SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
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when needed.
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@param[in] Pid Port ID of the SBI message
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@param[in] Offset Offset of the SBI message
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@param[in] Opcode Opcode
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@param[in] Posted Posted message
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@param[in] Fbe First byte enable
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@param[in] Bar Bar
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@param[in] Fid Function ID
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@param[in, out] Data32 Read/Write data
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@param[out] Response Response
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_DEVICE_ERROR Transaction fail
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@retval EFI_INVALID_PARAMETER Invalid parameter
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@retval EFI_TIMEOUT Timeout while waiting for response
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**/
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EFI_STATUS
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EFIAPI
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PchSbiExecutionEx (
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IN PCH_SBI_PID Pid,
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IN UINT64 Offset,
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IN PCH_SBI_OPCODE Opcode,
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IN BOOLEAN Posted,
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IN UINT16 Fbe,
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IN UINT16 Bar,
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IN UINT16 Fid,
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IN OUT UINT32 *Data32,
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OUT UINT8 *Response
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)
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{
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UINT64 P2sbBase;
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UINTN Timeout;
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UINT16 SbiStat;
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//
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// Check opcode valid
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//
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switch (Opcode) {
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case MemoryRead:
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case MemoryWrite:
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case PciConfigRead:
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case PciConfigWrite:
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case PrivateControlRead:
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case PrivateControlWrite:
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case GpioLockUnlock:
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break;
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default:
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return EFI_INVALID_PARAMETER;
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break;
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}
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P2sbBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_P2SB,
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PCI_FUNCTION_NUMBER_PCH_P2SB,
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0
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);
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if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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ASSERT (FALSE);
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return EFI_DEVICE_ERROR;
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}
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///
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/// BWG Section 2.2.1
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/// 1. Poll P2SB PCI offset D8h[0] = 0b
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/// Make sure the previous opeartion is completed.
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///
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Timeout = 0xFFFFFFF;
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while (Timeout > 0) {
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SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
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if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
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break;
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}
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Timeout--;
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}
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if (Timeout == 0) {
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return EFI_TIMEOUT;
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}
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//
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// Initial Response status
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//
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*Response = SBI_INVALID_RESPONSE;
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SbiStat = 0;
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///
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/// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Port ID
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///
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PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid << 24) | (UINT16) Offset));
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///
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/// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is expected to be 0 in PCH.
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///
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PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32) RShiftU64 (Offset, 16));
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///
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/// 5. Set P2SB PCI offset D8h[15:8] = 00000110b for read
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/// Set P2SB PCI offset D8h[15:8] = 00000111b for write
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//
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// Set SBISTAT[15:8] to the opcode passed in
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// Set SBISTAT[7] to the posted passed in
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//
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PciSegmentAndThenOr16 (
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(P2sbBase + R_P2SB_CFG_SBISTAT),
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(UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED),
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(UINT16) ((Opcode << 8) | (Posted << 7))
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);
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///
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/// 6. Write P2SB PCI offset DAh[15:0] = F000h
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///
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//
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// Set RID[15:0] = Fbe << 12 | Bar << 8 | Fid
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//
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PciSegmentWrite16 (
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(P2sbBase + R_P2SB_CFG_SBIRID),
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(((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF))
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);
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switch (Opcode) {
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case MemoryWrite:
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case PciConfigWrite:
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case PrivateControlWrite:
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case GpioLockUnlock:
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///
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/// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly
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///
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PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32);
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break;
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default:
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///
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/// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0,
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/// because all D0-DFh register range must be touched in PCH
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/// for a successful SBI transaction.
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///
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PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0);
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break;
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}
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///
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/// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] = 0b
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///
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//
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// Set SBISTAT[0] = 1b, trigger the SBI operation
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//
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PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16) B_P2SB_CFG_SBISTAT_INITRDY);
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//
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// Poll SBISTAT[0] = 0b, Polling for Busy bit
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//
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Timeout = 0xFFFFFFF;
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while (Timeout > 0) {
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SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
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if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
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break;
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}
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Timeout--;
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}
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if (Timeout == 0) {
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//
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// If timeout, it's fatal error.
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//
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return EFI_TIMEOUT;
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} else {
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///
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/// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction
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///
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*Response = (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2SB_CFG_SBISTAT_RESPONSE);
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if (*Response == SBI_SUCCESSFUL) {
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switch (Opcode) {
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case MemoryRead:
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case PciConfigRead:
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case PrivateControlRead:
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///
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/// 9. Read P2SB PCI offset D4h[31:0] for SBI data
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///
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*Data32 = PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA);
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break;
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default:
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break;
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}
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return EFI_SUCCESS;
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} else {
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return EFI_DEVICE_ERROR;
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}
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}
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}
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