/** @file
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This file contains routines for GPIO initialization
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "GpioLibrary.h"
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#include <Register/PchRegsPcr.h>
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//
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// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function
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// to cache values which will be programmed into respective GPIO registers
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// after all GpioPads are processed. This way MMIO accesses are decreased
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// and instead of doing one programming for one GpioPad there is only
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// one access for whole register.
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//
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typedef struct {
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UINT32 HostSoftOwnReg;
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UINT32 HostSoftOwnRegMask;
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UINT32 GpiGpeEnReg;
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UINT32 GpiGpeEnRegMask;
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UINT32 GpiNmiEnReg;
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UINT32 GpiNmiEnRegMask;
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UINT32 GpiSmiEnReg;
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UINT32 GpiSmiEnRegMask;
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UINT32 ConfigUnlockMask;
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UINT32 OutputUnlockMask;
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} GPIO_GROUP_DW_DATA;
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//
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// GPIO_GROUP_DW_NUMBER contains number of DWords required to
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// store Pad data for all groups. Each pad uses one bit.
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//
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// For Cannonlake only vGPIO group has >32 pads but those pads
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// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1
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//
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#define GPIO_GROUP_DW_NUMBER 1
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/**
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Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
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@param[in] PadNumber GPIO pad number
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@param[in] GpioConfig GPIO Config data
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@param[in out] DwRegsValues Values for GPIO DW Registers
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@retval None
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**/
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STATIC
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VOID
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GpioDwRegValueFromGpioConfig (
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IN UINT32 PadNumber,
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IN CONST GPIO_CONFIG *GpioConfig,
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IN OUT GPIO_GROUP_DW_DATA *GroupDwData
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)
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{
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UINT32 PadBitPosition;
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UINT32 DwNum;
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PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
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DwNum = GPIO_GET_DW_NUM (PadNumber);
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if (DwNum >= GPIO_GROUP_DW_NUMBER) {
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ASSERT (FALSE);
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return;
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}
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//
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// Update value to be programmed in HOSTSW_OWN register
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//
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GroupDwData[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
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GroupDwData[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
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//
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// Update value to be programmed in GPI_GPE_EN register
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//
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GroupDwData[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
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GroupDwData[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
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//
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// Update value to be programmed in GPI_NMI_EN register
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//
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GroupDwData[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
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GroupDwData[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
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//
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// Update value to be programmed in GPI_SMI_EN register
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GroupDwData[DwNum].GpiSmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
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GroupDwData[DwNum].GpiSmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntSmi) >> 2) << PadBitPosition;
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if ((GpioConfig->InterruptConfig & GpioIntSmi) == GpioIntSmi) {
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GroupDwData[DwNum].HostSoftOwnRegMask |= 1 << PadBitPosition;
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GroupDwData[DwNum].HostSoftOwnReg |= 1 << PadBitPosition;
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}
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//
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// Update information on Pad Configuration Lock
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//
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GroupDwData[DwNum].ConfigUnlockMask |= ((GpioConfig->LockConfig >> 1) & 0x1) << PadBitPosition;
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//
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// Update information on Pad Configuration Lock Tx
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//
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GroupDwData[DwNum].OutputUnlockMask |= ((GpioConfig->LockConfig >> 3) & 0x1) << PadBitPosition;
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//
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// if pad in GpioMode is an output default action should be to leave output unlocked
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//
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if ((GpioConfig->PadMode == GpioPadModeGpio) &&
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(GpioConfig->Direction == GpioDirOut) &&
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((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) == GpioLockDefault)) {
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GroupDwData[DwNum].OutputUnlockMask |= 0x1 << PadBitPosition;
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}
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}
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/**
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This internal procedure will scan GPIO initialization table and unlock
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all pads present in it
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@param[in] NumberOfItem Number of GPIO pad records in table
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@param[in] GpioInitTableAddress GPIO initialization table
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@param[in] Index Index of GPIO Initialization table record
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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STATIC
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EFI_STATUS
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GpioUnlockPadsForAGroup (
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IN UINT32 NumberOfItems,
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IN GPIO_INIT_CONFIG *GpioInitTableAddress,
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IN UINT32 Index
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)
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{
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UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER];
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UINT32 DwNum;
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UINT32 PadBitPosition;
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CONST GPIO_GROUP_INFO *GpioGroupInfo;
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UINT32 GpioGroupInfoLength;
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CONST GPIO_INIT_CONFIG *GpioData;
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GPIO_GROUP Group;
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UINT32 GroupIndex;
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UINT32 PadNumber;
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GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
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GpioData = &GpioInitTableAddress[Index];
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Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
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GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
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ZeroMem (PadsToUnlock, sizeof (PadsToUnlock));
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//
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// Loop through pads for one group. If pad belongs to a different group then
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// break and move to register programming.
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//
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while (Index < NumberOfItems) {
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GpioData = &GpioInitTableAddress[Index];
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if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
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//if next pad is from different group then break loop
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break;
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}
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PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
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//
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// Check if legal pin number
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//
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if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
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return EFI_INVALID_PARAMETER;
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}
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PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
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DwNum = GPIO_GET_DW_NUM (PadNumber);
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if (DwNum >= GPIO_GROUP_DW_NUMBER) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Update pads which need to be unlocked
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//
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PadsToUnlock[DwNum] |= 0x1 << PadBitPosition;
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//Move to next item
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Index++;
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}
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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//
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// Unlock pads
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//
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if (PadsToUnlock[DwNum] != 0) {
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GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
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GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This procedure will initialize multiple PCH GPIO pins
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@param[in] NumberofItem Number of GPIO pads to be updated
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@param[in] GpioInitTableAddress GPIO initialization table
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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STATIC
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EFI_STATUS
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GpioConfigurePch (
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IN UINT32 NumberOfItems,
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IN GPIO_INIT_CONFIG *GpioInitTableAddress
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)
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{
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UINT32 Index;
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UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER];
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UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER];
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UINT32 PadCfgReg;
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GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER];
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UINT32 DwNum;
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CONST GPIO_GROUP_INFO *GpioGroupInfo;
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UINT32 GpioGroupInfoLength;
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GPIO_PAD_OWN PadOwnVal;
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CONST GPIO_INIT_CONFIG *GpioData;
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UINT32 GroupIndex;
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UINT32 PadNumber;
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PCH_SBI_PID GpioCom;
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PadOwnVal = GpioPadOwnHost;
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GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
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Index = 0;
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while (Index < NumberOfItems) {
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GpioData = &GpioInitTableAddress[Index];
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GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
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GpioCom = GpioGroupInfo[GroupIndex].Community;
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DEBUG_CODE_BEGIN();
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if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioData->GpioPad));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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DEBUG_CODE_END ();
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//
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// Unlock pads for a given group which are going to be reconfigured
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//
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//
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// Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock settings
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// will get back to default only after G3 or DeepSx transition. On the other hand GpioPads
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// configuration is controlled by a configurable type of reset - PadRstCfg. This means that if
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// PadRstCfg != Powergood GpioPad will have its configuration locked despite it being not the
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// one desired by BIOS. Before reconfiguring all pads they will get unlocked.
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//
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GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index);
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ZeroMem (GroupDwData, sizeof (GroupDwData));
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//
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// Loop through pads for one group. If pad belongs to a different group then
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// break and move to register programming.
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//
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while (Index < NumberOfItems) {
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GpioData = &GpioInitTableAddress[Index];
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if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
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//if next pad is from different group then break loop
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break;
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}
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PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
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DEBUG_CODE_BEGIN ();
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//
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// Check if legal pin number
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//
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if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
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return EFI_INVALID_PARAMETER;
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}
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//
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// Check if selected GPIO Pad is not owned by CSME/ISH
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//
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GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
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if (PadOwnVal != GpioPadOwnHost) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
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DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
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//Move to next item
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Index++;
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continue;
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}
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//
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// Check if Pad enabled for SCI is to be in unlocked state
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//
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if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) == GpioIntSci) &&
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((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) != GpioPadConfigUnlock)){
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: %a used for SCI is not unlocked!\n", GpioName (GpioData->GpioPad)));
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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DEBUG_CODE_END ();
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ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
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ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
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//
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// Get GPIO PADCFG register value from GPIO config data
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//
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GpioPadCfgRegValueFromGpioConfig (
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GpioData->GpioPad,
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&GpioData->GpioConfig,
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PadCfgDwReg,
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PadCfgDwRegMask
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);
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//
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// Create PADCFG register offset using group and pad number
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//
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PadCfgReg = S_GPIO_PCR_PADCFG * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset;
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//
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// Write PADCFG DW0 register
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//
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, PadCfgReg),
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~PadCfgDwRegMask[0],
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PadCfgDwReg[0]
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);
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//
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// Write PADCFG DW1 register
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//
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, PadCfgReg + 0x4),
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~PadCfgDwRegMask[1],
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PadCfgDwReg[1]
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);
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//
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// Write PADCFG DW2 register
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//
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, PadCfgReg + 0x8),
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~PadCfgDwRegMask[2],
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PadCfgDwReg[2]
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);
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//
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// Get GPIO DW register values from GPIO config data
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//
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GpioDwRegValueFromGpioConfig (
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PadNumber,
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&GpioData->GpioConfig,
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GroupDwData
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);
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//Move to next item
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Index++;
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}
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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//
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// Write HOSTSW_OWN registers
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//
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if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4),
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~GroupDwData[DwNum].HostSoftOwnRegMask,
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GroupDwData[DwNum].HostSoftOwnReg
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);
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}
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//
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// Write GPI_GPE_EN registers
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//
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if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4),
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~GroupDwData[DwNum].GpiGpeEnRegMask,
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GroupDwData[DwNum].GpiGpeEnReg
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);
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}
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//
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// Write GPI_NMI_EN registers
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//
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if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4),
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~GroupDwData[DwNum].GpiNmiEnRegMask,
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GroupDwData[DwNum].GpiNmiEnReg
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);
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} else if (GroupDwData[DwNum].GpiNmiEnReg != 0x0) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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}
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//
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// Write GPI_SMI_EN registers
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//
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if (GpioGroupInfo[GroupIndex].SmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].SmiEnOffset + DwNum * 0x4),
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~GroupDwData[DwNum].GpiSmiEnRegMask,
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GroupDwData[DwNum].GpiSmiEnReg
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);
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} else if (GroupDwData[DwNum].GpiSmiEnReg != 0x0) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting SMI\n", GroupIndex));
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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}
|
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//
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// Update Pad Configuration unlock data
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//
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if (GroupDwData[DwNum].ConfigUnlockMask) {
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GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwData[DwNum].ConfigUnlockMask);
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}
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//
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// Update Pad Output unlock data
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//
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if (GroupDwData[DwNum].OutputUnlockMask) {
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GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[DwNum].OutputUnlockMask);
|
}
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}
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}
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return EFI_SUCCESS;
|
}
|
|
/**
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This procedure will clear all status bits of any GPIO interrupts.
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**/
|
STATIC
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VOID
|
GpioClearAllGpioInterrupts (
|
VOID
|
)
|
{
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GPIO_GROUP Group;
|
CONST GPIO_GROUP_INFO *GpioGroupInfo;
|
GPIO_GROUP GpioGroupLowest;
|
GPIO_GROUP GpioGroupHighest;
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UINT32 GroupIndex;
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UINT32 GpioGroupInfoLength;
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UINT32 DwNum;
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|
GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
|
|
GpioGroupLowest = GpioGetLowestGroup ();
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GpioGroupHighest = GpioGetHighestGroup ();
|
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for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
|
GroupIndex = GpioGetGroupIndexFromGroup (Group);
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//
|
// Check if group has GPI IS register
|
//
|
if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
|
//
|
// Clear all GPI_IS Status bits by writing '1'
|
//
|
for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
|
MmioWrite32 (
|
PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4),
|
0xFFFFFFFF
|
);
|
}
|
}
|
|
//
|
// Check if group has GPI_GPE_STS register
|
//
|
if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
|
//
|
// Clear all GPI_GPE_STS Status bits by writing '1'
|
//
|
for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
|
MmioWrite32 (
|
PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4),
|
0xFFFFFFFF
|
);
|
}
|
}
|
|
//
|
// Check if group has SMI_STS register
|
//
|
if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
|
//
|
// Clear all SMI_STS Status bits by writing '1'
|
//
|
for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
|
MmioWrite32 (
|
PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4),
|
0xFFFFFFFF
|
);
|
}
|
}
|
|
//
|
// Check if group has NMI_STS register
|
//
|
if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
|
//
|
// Clear all NMI_STS Status bits by writing '1'
|
//
|
for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
|
MmioWrite32 (
|
PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4),
|
0xFFFFFFFF
|
);
|
}
|
}
|
|
}
|
}
|
|
/**
|
This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
|
Structure contains fields that can be used to configure each pad.
|
Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
|
Separate fields could be set to hardware default if it does not matter, except
|
GpioPad and PadMode.
|
Function will work in most efficient way if pads which belong to the same group are
|
placed in adjacent records of the table.
|
Although function can enable pads for Native mode, such programming is done
|
by reference code when enabling related silicon feature.
|
|
@param[in] NumberofItem Number of GPIO pads to be updated
|
@param[in] GpioInitTableAddress GPIO initialization table
|
|
@retval EFI_SUCCESS The function completed successfully
|
@retval EFI_INVALID_PARAMETER Invalid group or pad number
|
**/
|
EFI_STATUS
|
GpioConfigurePads (
|
IN UINT32 NumberOfItems,
|
IN GPIO_INIT_CONFIG *GpioInitTableAddress
|
)
|
{
|
EFI_STATUS Status;
|
Status = GpioConfigurePch (NumberOfItems, GpioInitTableAddress);
|
GpioClearAllGpioInterrupts ();
|
return Status;
|
}
|
|
