/** @file
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Register names for PCH Integrated Sensor Hub (ISH3.0)
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_ISH_H_
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#define _PCH_REGS_ISH_H_
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//
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// ISH Controller Registers
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//
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// D19:F0
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#define PCI_DEVICE_NUMBER_PCH_ISH 19
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#define PCI_FUNCTION_NUMBER_PCH_ISH 0
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// PCI Configuration Space Registers
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#define R_ISH_CFG_BAR0_LOW 0x10
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#define R_ISH_CFG_BAR0_HIGH 0x14
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#define V_ISH_CFG_BAR0_SIZE 0x100000
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#define N_ISH_CFG_BAR0_ALIGNMENT 20
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#define R_ISH_CFG_BAR1_LOW 0x18
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#define R_ISH_CFG_BAR1_HIGH 0x1C
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#define V_ISH_CFG_BAR1_SIZE 0x1000
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#define N_ISH_CFG_BAR1_ALIGNMENT 12
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//
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// ISH Private Configuration Space Registers (IOSF2OCP)
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// (PID:ISH)
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//
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#define R_ISH_PCR_PMCTL 0x1D0 ///< Power Management
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#define R_ISH_PCR_PCICFGCTRL 0x200 ///< PCI Configuration Control
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#define B_ISH_PCR_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number
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#define N_ISH_PCR_PCICFGCTR_PCI_IRQ 20
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#define B_ISH_PCR_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number
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#define N_ISH_PCR_PCICFGCTR_ACPI_IRQ 12
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#define B_ISH_PCR_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin
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#define N_ISH_PCR_PCICFGCTR_IPIN1 8
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#define B_ISH_PCR_PCICFGCTRL_BAR1DIS BIT7 ///< BAR1 Disable
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//
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// Number of pins used by ISH controllers
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//
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#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2
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#define PCH_ISH_PINS_PER_UART_CONTROLLER 4
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#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4
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#endif
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