/** @file
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Register names for PCH GPIO
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_GPIO_H_
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#define _PCH_REGS_GPIO_H_
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//
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// GPIO Common Private Configuration Registers
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//
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#define R_GPIO_PCR_REV_ID 0x00
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#define R_GPIO_PCR_CAP_LIST 0x04
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#define R_GPIO_PCR_FAMBAR 0x08
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#define R_GPIO_PCR_PADBAR 0x0C
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#define B_GPIO_PCR_PADBAR 0x0000FFFF
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#define R_GPIO_PCR_MISCCFG 0x10
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#define B_GPIO_PCR_MISCCFG_IRQ_ROUTE 0xFF000000
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#define N_GPIO_PCR_MISCCFG_IRQ_ROUTE 24
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#define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
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#define N_GPIO_PCR_MISCCFG_GPE0_DW2 16
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#define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
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#define N_GPIO_PCR_MISCCFG_GPE0_DW1 12
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#define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
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#define N_GPIO_PCR_MISCCFG_GPE0_DW0 8
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#define B_GPIO_PCR_MISCCFG_GPSIDEDPCGEN BIT5
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#define B_GPIO_PCR_MISCCFG_GPRCOMPCDLCGEN BIT4
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#define B_GPIO_PCR_MISCCFG_GPRTCDLCGEN BIT3
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#define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1
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#define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0
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//
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// GPIO SerialBlink/PWM registers
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//
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#define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200
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#define R_GPIO_PCR_PWMC 0x0204
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#define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208
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#define R_GPIO_PCR_GP_SER_BLINK 0x020C
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#define B_GPIO_PCR_GP_SER_BLINK 0x1F
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#define R_GPIO_PCR_GP_SER_CMDSTS 0x0210
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#define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22)
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#define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22
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#define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000
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#define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16
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#define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8
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#define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0
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#define R_GPIO_PCR_GP_SER_DATA 0x0210
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//
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// PADCFG register is split into multiple DW registers
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// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
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//
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#define S_GPIO_PCR_PADCFG 0x10
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//
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// Pad Configuration Register DW0
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//
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//Pad Reset Config
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#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)
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#define N_GPIO_PCR_RST_CONF 30
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#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00
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#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01
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#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02
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#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
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//RX Pad State Select
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#define B_GPIO_PCR_RX_PAD_STATE BIT29
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#define N_GPIO_PCR_RX_PAD_STATE 29
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#define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00
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#define V_GPIO_PCR_RX_PAD_STATE_INT 0x01
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//RX Raw Overrride to 1
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#define B_GPIO_PCR_RX_RAW1 BIT28
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#define N_GPIO_PCR_RX_RAW1 28
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#define V_GPIO_PCR_RX_RAW1_DIS 0x00
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#define V_GPIO_PCR_RX_RAW1_EN 0x01
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//RX Level/Edge Configuration
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#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
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#define N_GPIO_PCR_RX_LVL_EDG 25
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#define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00
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#define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01
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#define V_GPIO_PCR_RX_LVL_EDG_0 0x02
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#define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03
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//RX Invert
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#define B_GPIO_PCR_RXINV BIT23
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#define N_GPIO_PCR_RXINV 23
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#define V_GPIO_PCR_RXINV_NO 0x00
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#define V_GPIO_PCR_RXINV_YES 0x01
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//GPIO Input Route IOxAPIC
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#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
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#define N_GPIO_PCR_RX_APIC_ROUTE 20
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#define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01
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//GPIO Input Route SCI
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#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
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#define N_GPIO_PCR_RX_SCI_ROUTE 19
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#define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01
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//GPIO Input Route SMI
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#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
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#define N_GPIO_PCR_RX_SMI_ROUTE 18
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#define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01
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//GPIO Input Route NMI
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#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
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#define N_GPIO_PCR_RX_NMI_ROUTE 17
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#define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01
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//GPIO Pad Mode
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#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
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#define N_GPIO_PCR_PAD_MODE 10
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#define V_GPIO_PCR_PAD_MODE_GPIO 0
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#define V_GPIO_PCR_PAD_MODE_NAT_1 1
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#define V_GPIO_PCR_PAD_MODE_NAT_2 2
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#define V_GPIO_PCR_PAD_MODE_NAT_3 3
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#define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only
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//GPIO RX Disable
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#define B_GPIO_PCR_RXDIS BIT9
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#define N_GPIO_PCR_RXDIS 9
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#define V_GPIO_PCR_RXDIS_EN 0x00
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#define V_GPIO_PCR_RXDIS_DIS 0x01
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//GPIO TX Disable
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#define B_GPIO_PCR_TXDIS BIT8
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#define N_GPIO_PCR_TXDIS 8
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#define V_GPIO_PCR_TXDIS_EN 0x00
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#define V_GPIO_PCR_TXDIS_DIS 0x01
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//GPIO RX State
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#define B_GPIO_PCR_RX_STATE BIT1
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#define N_GPIO_PCR_RX_STATE 1
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#define V_GPIO_PCR_RX_STATE_LOW 0x00
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#define V_GPIO_PCR_RX_STATE_HIGH 0x01
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//GPIO TX State
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#define B_GPIO_PCR_TX_STATE BIT0
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#define N_GPIO_PCR_TX_STATE 0
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#define V_GPIO_PCR_TX_STATE_LOW 0x00
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#define V_GPIO_PCR_TX_STATE_HIGH 0x01
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//
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// Pad Configuration Register DW1
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//
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//Padtol
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#define B_GPIO_PCR_PADTOL BIT25
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#define N_GPIO_PCR_PADTOL 25
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#define V_GPIO_PCR_PADTOL_NONE 0x00
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#define V_GPIO_PCR_PADTOL_CLEAR 0x00
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#define V_GPIO_PCR_PADTOL_SET 0x01
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//Termination
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#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
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#define N_GPIO_PCR_TERM 10
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#define V_GPIO_PCR_TERM_WPD_NONE 0x00
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#define V_GPIO_PCR_TERM_WPD_5K 0x02
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#define V_GPIO_PCR_TERM_WPD_20K 0x04
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#define V_GPIO_PCR_TERM_WPU_NONE 0x08
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#define V_GPIO_PCR_TERM_WPU_1K 0x09
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#define V_GPIO_PCR_TERM_WPU_2K 0x0B
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#define V_GPIO_PCR_TERM_WPU_5K 0x0A
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#define V_GPIO_PCR_TERM_WPU_20K 0x0C
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#define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D
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#define V_GPIO_PCR_TERM_NATIVE 0x0F
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//Interrupt number
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#define B_GPIO_PCR_INTSEL 0x7F
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#define N_GPIO_PCR_INTSEL 0
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//
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//Debounce
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#define B_GPIO_PCR_DEBOUNCE (BIT4 | BIT3 | BIT2 | BIT1)
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#define N_GPIO_PCR_DEBOUNCE 1
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//Debounce Enable
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#define B_GPIO_PCR_DEBEN BIT0
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#define N_GPIO_PCR_DEBEN 0
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//
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// Ownership
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//
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#define V_GPIO_PCR_OWN_GPIO 0x01
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#define V_GPIO_PCR_OWN_ACPI 0x00
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//
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// GPE
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//
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#define V_GPIO_PCR_GPE_EN 0x01
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#define V_GPIO_PCR_GPE_DIS 0x00
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//
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// SMI
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//
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#define V_GPIO_PCR_SMI_EN 0x01
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#define V_GPIO_PCR_SMI_DIS 0x00
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//
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// NMI
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//
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#define V_GPIO_PCR_NMI_EN 0x01
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#define V_GPIO_PCR_NMI_DIS 0x00
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//
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// GPIO native features pins data
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//
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#define PCH_GPIO_HDA_LINK_NUMBER_OF_PINS 6
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#define PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS 2
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#define PCH_GPIO_HDA_SSP_NUMBER_OF_PINS 4
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#define PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS 2
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#define PCH_GPIO_SMBUS_NUMBER_OF_PINS 2
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#define PCH_GPIO_CPU_GP_NUMBER_OF_PINS 4
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#define PCH_GPIO_EDP_NUMBER_OF_PINS 4
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#define PCH_GPIO_DDSP_HPD_NUMBER_OF_PINS 4
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#define PCH_GPIO_DDP_NUMBER_OF_INTERFACES 4
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#define PCH_GPIO_DDP_NUMBER_OF_PINS 2
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#define PCH_GPIO_CNVI_UART_NUMBER_OF_PINS 4
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#define PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS 4
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#define PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS 4
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///
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/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
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/// Below defines are to be used internally by PCH SMI dispatcher only
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///
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#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
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#define S_GPIO_PCR_GP_SMI_EN 4
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#define S_GPIO_PCR_GP_SMI_STS 4
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///
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/// Groups mapped to 2-tier General Purpose Event will all be under
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/// one master GPE_111 (0x6F)
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///
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#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
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#endif
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