/** @file
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Register names for DMI and OP-DMI
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_DMI_H_
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#define _PCH_REGS_DMI_H_
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//
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// DMI Chipset Configuration Registers (PID:DMI)
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//
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//
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// VC Configuration (Common)
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//
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#define B_PCH_DMI_PCR_V0CTL_EN BIT31
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#define B_PCH_DMI_PCR_V0CTL_ID (7 << 24) ///< Bit[26:24]
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#define N_PCH_DMI_PCR_V0CTL_ID 24
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#define V_PCH_DMI_PCR_V0CTL_ETVM_MASK 0xFC00
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#define V_PCH_DMI_PCR_V0CTL_TVM_MASK 0x7E
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#define B_PCH_DMI_PCR_V0STS_NP BIT1
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#define B_PCH_DMI_PCR_V1CTL_EN BIT31
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#define B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24) ///< Bit[27:24]
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#define N_PCH_DMI_PCR_V1CTL_ID 24
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#define V_PCH_DMI_PCR_V1CTL_ETVM_MASK 0xFC00
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#define V_PCH_DMI_PCR_V1CTL_TVM_MASK 0xFE
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#define B_PCH_DMI_PCR_V1STS_NP BIT1
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//
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// DMI Source Decode PCRs (Common)
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//
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#define R_PCH_DMI_PCR_PCIEPAR1E 0x2700 ///< PCIE Port IOxAPIC Range 1 Enable
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#define R_PCH_DMI_PCR_PCIEPAR2E 0x2704 ///< PCIE Port IOxAPIC Range 2 Enable
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#define R_PCH_DMI_PCR_PCIEPAR3E 0x2708 ///< PCIE Port IOxAPIC Range 3 Enable
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#define R_PCH_DMI_PCR_PCIEPAR4E 0x270C ///< PCIE Port IOxAPIC Range 4 Enable
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#define R_PCH_DMI_PCR_PCIEPAR1DID 0x2710 ///< PCIE Port IOxAPIC Range 1 Destination ID
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#define R_PCH_DMI_PCR_PCIEPAR2DID 0x2714 ///< PCIE Port IOxAPIC Range 2 Destination ID
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#define R_PCH_DMI_PCR_PCIEPAR3DID 0x2718 ///< PCIE Port IOxAPIC Range 3 Destination ID
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#define R_PCH_DMI_PCR_PCIEPAR4DID 0x271C ///< PCIE Port IOxAPIC Range 4 Destination ID
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#define R_PCH_DMI_PCR_P2SBIOR 0x2720 ///< P2SB IO Range
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#define R_PCH_DMI_PCR_TTTBARB 0x2724 ///< Thermal Throttling BIOS Assigned Thermal Base Address
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#define R_PCH_DMI_PCR_TTTBARBH 0x2728 ///< Thermal Throttling BIOS Assigned Thermal Base High Address
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#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 ///< LPC Generic I/O Range 1
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#define R_PCH_DMI_PCR_LPCLGIR2 0x2734 ///< LPC Generic I/O Range 2
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#define R_PCH_DMI_PCR_LPCLGIR3 0x2738 ///< LPC Generic I/O Range 3
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#define R_PCH_DMI_PCR_LPCLGIR4 0x273C ///< LPC Generic I/O Range 4
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#define R_PCH_DMI_PCR_LPCGMR 0x2740 ///< LPC Generic Memory Range
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#define R_PCH_DMI_PCR_SEGIR 0x27BC ///< Second ESPI Generic I/O Range
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#define R_PCH_DMI_PCR_SEGMR 0x27C0 ///< Second ESPI Generic Memory Range
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#define R_PCH_DMI_PCR_LPCBDE 0x2744 ///< LPC BIOS Decode Enable
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#define R_PCH_DMI_PCR_UCPR 0x2748 ///< uCode Patch Region
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#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 ///< uCode Patch Region Enable
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#define R_PCH_DMI_PCR_GCS 0x274C ///< Generic Control and Status
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#define B_PCH_DMI_PCR_RPRDID 0xFFFF0000 ///< RPR Destination ID
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#define B_PCH_DMI_PCR_BBS BIT10 ///< Boot BIOS Strap
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#define B_PCH_DMI_PCR_RPR BIT11 ///< Reserved Page Route
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#define B_PCH_DMI_PCR_BILD BIT0 ///< BIOS Interface Lock-Down
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#define R_PCH_DMI_PCR_IOT1 0x2750 ///< I/O Trap Register 1
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#define R_PCH_DMI_PCR_IOT2 0x2758 ///< I/O Trap Register 2
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#define R_PCH_DMI_PCR_IOT3 0x2760 ///< I/O Trap Register 3
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#define R_PCH_DMI_PCR_IOT4 0x2768 ///< I/O Trap Register 4
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#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
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#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
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#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
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#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
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#define R_PCH_DMI_PCR_GPMR1 0x277C ///< General Purpose Memory Range 1
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#define R_PCH_DMI_PCR_GPMR1DID 0x2780 ///< General Purpose Memory Range 1 Destination ID
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#define R_PCH_DMI_PCR_GPMR2 0x2784 ///< General Purpose Memory Range 2
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#define R_PCH_DMI_PCR_GPMR2DID 0x2788 ///< General Purpose Memory Range 2 Destination ID
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#define R_PCH_DMI_PCR_GPMR3 0x278C ///< General Purpose Memory Range 3
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#define R_PCH_DMI_PCR_GPMR3DID 0x2790 ///< General Purpose Memory Range 3 Destination ID
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#define R_PCH_DMI_PCR_GPIOR1 0x2794 ///< General Purpose I/O Range 1
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#define R_PCH_DMI_PCR_GPIOR1DID 0x2798 ///< General Purpose I/O Range 1 Destination ID
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#define R_PCH_DMI_PCR_GPIOR2 0x279C ///< General Purpose I/O Range 2
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#define R_PCH_DMI_PCR_GPIOR2DID 0x27A0 ///< General Purpose I/O Range 2 Destination ID
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#define R_PCH_DMI_PCR_GPIOR3 0x27A4 ///< General Purpose I/O Range 3
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#define R_PCH_DMI_PCR_GPIOR3DID 0x27A8 ///< General Purpose I/O Range 3 Destination ID
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//
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// Opi PHY registers
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//
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#define R_PCH_OPIPHY_PCR_0110 0x0110
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#define R_PCH_OPIPHY_PCR_0118 0x0118
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#define R_PCH_OPIPHY_PCR_011C 0x011C
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#define R_PCH_OPIPHY_PCR_0354 0x0354
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#define R_PCH_OPIPHY_PCR_B104 0xB104
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#define R_PCH_OPIPHY_PCR_B10C 0xB10C
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#endif
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