/** @file
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The GUID definition for PchConfigHob
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_CONFIG_HOB_H_
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#define _PCH_CONFIG_HOB_H_
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#include <ConfigBlock.h>
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#include <ConfigBlock/SmbusConfig.h>
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#include <ConfigBlock/InterruptConfig.h>
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#include <ConfigBlock/PcieRpConfig.h>
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#include <ConfigBlock/SataConfig.h>
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#include <ConfigBlock/FlashProtectionConfig.h>
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extern EFI_GUID gPchConfigHobGuid;
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#pragma pack (push,1)
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///
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/// This structure contains the HOB which are related to PCH general config.
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///
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typedef struct {
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/**
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This member describes whether or not the Compatibility Revision ID (CRID) feature
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of PCH should be enabled. <b>0: Disable</b>; 1: Enable
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**/
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UINT32 Crid : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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///
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///
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} GENERAL_HOB;
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///
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/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
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///
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typedef struct {
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UINT8 RsvdBytes[3];
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UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
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/**
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Array of addresses reserved for non-ARP-capable SMBus devices.
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**/
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UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
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} SMBUS_HOB;
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///
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/// The INTERRUPT describes interrupt settings for PCH HOB.
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///
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typedef struct {
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UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
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UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
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UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4.
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PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
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UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< PCI interrupt routing for 8259 PIC controller
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} INTERRUPT_HOB;
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///
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/// The CNVI_HOB block describes CNVi device.
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///
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typedef struct {
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UINT32 Mode : 1; ///< 0: Disabled, <b>1: Auto</b>
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UINT32 RsvdBits0 : 31;
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} CNVI_HOB;
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/**
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The SERIAL_IO block provides the configurations to set the Serial IO controllers
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**/
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typedef struct {
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/**
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0: Disabled;
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- Device is placed in D3
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- Gpio configuration is skipped
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- Device will be disabled in PSF
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- !important! If given device is Function 0 and not all other LPSS functions on given device
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are disabled, then PSF disabling is skipped.
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PSF default will remain and device PCI CFG Space will still be visible.
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This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
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<b>1: Pci</b>;
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- Gpio pin configuration in native mode for each assigned pin
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RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
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- Device will be enabled in PSF
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- Only Bar 0 will be enabled
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2: Acpi;
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- Gpio pin configuration in native mode for each assigned pin
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RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
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- Device will be hidden in PSF and not available to PCI enumerator
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- Both BARs are enabled, BAR1 becomes devices Pci config Space
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@note Intel does not provide Windows SerialIo drivers for this mode
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3: Hidden;
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Designated for Kernel Debug and Legacy UART configuartion, might also be used for IO Expander on I2C
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- Device is placed in D0
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- Gpio pin configuration in native mode for each assigned pin
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RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
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- Device will be hidden in PSF and not available to PCI enumerator
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- Both BARs are enabled, BAR1 becomes devices Pci config Space
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- !important! In this mode UART will work in 16550 Legacy 8BIT Mode, it's resources will be assigned to mother board through ACPI (PNP0C02)
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@note Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNumber for all SerialIo UARTx,
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the PCD is more meaningful to represent the board design. It means, if PcdSerialIoUartDebugEnable is not 0,
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the board is designed to use the SerialIo UART for debug message and the PcdSerialIoUartNumber is dedicated
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to be Debug UART usage. Therefore, it should grayout the option from setup menu since no other options
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available for this UART controller on this board, and also override the policy default accordingly.
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While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure the UART controller by policy.
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**/
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UINT8 DevMode[PCH_MAX_SERIALIO_CONTROLLERS];
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UINT32 DebugUartNumber : 2; ///< UART number for debug purpose. 0:UART0, 1: UART1, <b>2:UART2</b>
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UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug UART controller after post. 0: disabled, <b>1: enabled</b>
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UINT32 RsvdBits0 : 29;
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} SERIAL_IO_HOB;
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///
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/// The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
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///
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typedef struct {
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///
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/// These members describe the configuration of each PCH PCIe root port.
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///
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PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
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/**
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This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
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or leaving untouched.
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- <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b>
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- To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are
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presented for maximum power savings where possible.
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- To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device
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functionality.
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- 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability.
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**/
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UINT32 AllowNoLtrIccPllShutdown : 1;
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UINT32 RsvdBits0 : 31;
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} PCIERP_HOB;
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typedef struct {
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UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
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UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initiated by a codec in Sx, <b>0: Disable</b>; 1: Enable
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UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with HDA
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UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with SSP1
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UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with DMIC1
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UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with DMIC0
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UINT32 RsvdBits0 : 26; ///< Reserved bits
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} HDAUDIO_HOB;
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typedef struct {
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///
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/// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
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///
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UINT32 Enable : 1;
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UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
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UINT32 RsvdBits0 : 30; ///< Reserved bits
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/**
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This member configures the features, property, and capability for each SATA port.
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**/
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PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
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/**
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This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
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**/
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PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
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} SATA_HOB;
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///
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/// The SCS_HOB block describes Storage and Communication Subsystem (SCS) settings for PCH.
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///
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typedef struct {
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UINT32 ScsEmmcEnabled : 2; ///< Determine if eMMC is enabled - 0: Disabled, <b>1: Enabled</b>.
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UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC HS400 Mode if ScsEmmcEnabled - <b>0: Disabled</b>, 1: Enabled
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/**
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Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid. <b>0: Disabled</b>, 1: Enabled.
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First Boot or CMOS clear, system boot with Default settings, set tuning required.
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Subsequent Boots, Get Variable 'Hs400TuningData'
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- if failed to get variable, set tuning required
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- if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxDataDll from variable. Set tuning not required.
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**/
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UINT32 ScsEmmcHs400TuningRequired : 1;
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UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tuning Data Valid
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UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver strength: <b>0 - 33 Ohm</b>, 1 - 40 Ohm, 2 - 50 Ohm
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UINT32 ScsSdPowerEnableActiveHigh : 1; ///< Sd PWREN# active high
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UINT32 ScsSdCardEnabled : 1; ///< Sd card enabled
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UINT32 RsvdBits : 22;
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} SCS_HOB;
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/**
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The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
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for security requirement.
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**/
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typedef struct {
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UINT32 GlobalSmi : 1;
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/**
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<b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
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Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>.
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**/
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UINT32 BiosInterface : 1;
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/**
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Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
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and lower 128-byte bank of RTC RAM. 0: Disable; <b>1: Enable</b>.
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**/
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UINT32 RtcMemoryLock : 1;
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/**
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Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
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for the BIOS region protection. When it is enabled, the BIOS Region can only be
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modified from SMM after EndOfDxe protocol is installed.
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Note: When BiosLock is enabled, platform code also needs to update to take care
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of BIOS modification (including SetVariable) in DXE or runtime phase after
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EndOfDxe protocol is installed.
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Enable InSMM.STS (EISS) in SPI
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If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
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in order to write to BIOS regions of SPI Flash. If this EISS bit is clear,
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then the InSMM.STS is a don't care.
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The BIOS must set the EISS bit while BIOS Guard support is enabled.
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In recovery path, platform can temporary disable EISS for SPI programming in
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PEI phase or early DXE phase.
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0: Disable; <b>1: Enable.</b>
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**/
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UINT32 BiosLock : 1;
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UINT32 RsvdBits : 28;
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} LOCK_DOWN_HOB;
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/**
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The PM_HOB block describes expected miscellaneous power management settings.
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The PowerResetStatusClear field would clear the Power/Reset status bits, please
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set the bits if you want PCH Init driver to clear it, if you want to check the
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status later then clear the bits.
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**/
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typedef struct {
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UINT32 SlpS0VmRuntimeControl : 1; /// < SLP_S0 Voltage Margining Runtime Control. <b>0: Disable</b>; 1: Enable.
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UINT32 SlpS0Vm070VSupport : 1; /// < SLP_S0 0.70V Voltage Margining Support. <b>0: Disable</b>; 1: Enable.
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UINT32 SlpS0Vm075VSupport : 1; /// < SLP_S0 0.75V Voltage Margining Support. <b>0: Disable</b>; 1: Enable.
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UINT32 PsOnEnable : 1; /// < Indicates if PS_ON support has been enabled, <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits1 : 28;
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} PM_HOB;
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/**
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PCH Trace Hub HOB settings.
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**/
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typedef struct {
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UINT32 PchTraceHubMode : 2; // <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode
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UINT32 Rsvd1 : 30; // Reserved bytes
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} PCH_TRACEHUB_HOB;
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/**
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PCH eSPI HOB settings.
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**/
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typedef struct {
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UINT32 BmeMasterSlaveEnabled : 1; // <b>0 = BME disable</b>; 1 = BME enable
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UINT32 RsvdBits : 31;
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} PCH_ESPI_HOB;
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///
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/// Pch Config Hob
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///
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for gPchConfigHobGuid
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GENERAL_HOB General; ///< Pch general HOB definition
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INTERRUPT_HOB Interrupt; ///< Interrupt HOB definition
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SERIAL_IO_HOB SerialIo; ///< Serial io HOB definition
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PCIERP_HOB PcieRp; ///< PCIE root port HOB definition
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SCS_HOB Scs; ///< Scs HOB definition
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CNVI_HOB Cnvi; ///< Cnvi Hob definition
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LOCK_DOWN_HOB LockDown; ///< Lock down HOB definition
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PM_HOB Pm; ///< PM HOB definition
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HDAUDIO_HOB HdAudio; ///< HD audio definition
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SATA_HOB Sata[PCH_MAX_SATA_CONTROLLERS]; ///< SATA definition
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PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];
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SMBUS_HOB Smbus;
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PCH_TRACEHUB_HOB PchTraceHub; ///< PCH Trace Hub definition
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PCH_ESPI_HOB Espi; ///< PCH eSPI definition
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} PCH_CONFIG_HOB;
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#pragma pack (pop)
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#endif
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