/** @file
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Build time limits of PCH resources.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_LIMITS_H_
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#define _PCH_LIMITS_H_
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//
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// PCIe limits
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//
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#define PCH_MAX_PCIE_ROOT_PORTS 24
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#define PCH_MAX_PCIE_CONTROLLERS 6
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//
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// PCIe clocks limits
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//
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#define PCH_MAX_PCIE_CLOCKS 16
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//
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// RST PCIe Storage Cycle Router limits
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//
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#define PCH_MAX_RST_PCIE_STORAGE_CR 3
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//
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// SATA limits
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//
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#define PCH_MAX_SATA_CONTROLLERS 3
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#define PCH_MAX_SATA_PORTS 8
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//
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// USB limits
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//
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#define PCH_MAX_USB2_PORTS 16
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#define PCH_MAX_USB3_PORTS 10
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//
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// SerialIo limits
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//
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#define PCH_MAX_SERIALIO_CONTROLLERS 12
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#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 6
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#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 3
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#define PCH_MAX_SERIALIO_UART_CONTROLLERS 3
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//
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// Number of eSPI slaves
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//
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#define PCH_MAX_ESPI_SLAVES 2
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#endif // _PCH_LIMITS_H_
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