/** @file
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Serial IO policy
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SERIAL_IO_CONFIG_H_
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#define _SERIAL_IO_CONFIG_H_
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#define SERIAL_IO_CONFIG_REVISION 2
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extern EFI_GUID gSerialIoConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH_SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Add I2cPadsTermination
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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0: Disabled;
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- Device is placed in D3
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- Gpio configuration is skipped
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- Device will be disabled in PSF
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- !important! If given device is Function 0 and not all other LPSS functions on given device
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are disabled, then PSF disabling is skipped.
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PSF default will remain and device PCI CFG Space will still be visible.
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This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
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<b>1: Pci</b>;
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- Gpio pin configuration in native mode for each assigned pin
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RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
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- Device will be enabled in PSF
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- Only Bar 0 will be enabled
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2: Acpi;
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- Gpio pin configuration in native mode for each assigned pin
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RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
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- Device will be hidden in PSF and not available to PCI enumerator
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- Both BARs are enabled, BAR1 becomes devices Pci config Space
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@note Intel does not provide Windows SerialIo drivers for this mode
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3: Hidden;
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Designated for Kernel Debug and Legacy UART configuartion, might also be used for IO Expander on I2C
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- Device is placed in D0
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- Gpio pin configuration in native mode for each assigned pin
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RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
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- Device will be hidden in PSF and not available to PCI enumerator
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- Both BARs are enabled, BAR1 becomes devices Pci config Space
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- !important! In this mode UART will work in 16550 Legacy 8BIT Mode, it's resources will be assigned to mother board through ACPI (PNP0C02)
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@note Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNumber for all SerialIo UARTx,
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the PCD is more meaningful to represent the board design. It means, if PcdSerialIoUartDebugEnable is not 0,
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the board is designed to use the SerialIo UART for debug message and the PcdSerialIoUartNumber is dedicated
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to be Debug UART usage. Therefore, it should grayout the option from setup menu since no other options
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available for this UART controller on this board, and also override the policy default accordingly.
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While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure the UART controller by policy.
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**/
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UINT8 DevMode[PCH_MAX_SERIALIO_CONTROLLERS];
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UINT8 SpiCsPolarity[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< Selects SPI ChipSelect signal polarity, <b>0=active low</b>.
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UINT8 UartHwFlowCtrl[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< Enables UART hardware flow control, CTS and RTS lines, <b>0:disabled</b>, 1:enabled
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/**
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I2C Pads Internal Termination.
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For more information please see Platform Design Guide.
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Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
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<b>GpioTermNone: No termination</b>,
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GpioTermWpu1K: 1kOhm weak pull-up,
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GpioTermWpu5K: 5kOhm weak pull-up,
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GpioTermWpu20K: 20kOhm weak pull-up
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**/
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UINT8 I2cPadsTermination[PCH_MAX_SERIALIO_I2C_CONTROLLERS];
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/**
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UART device for debug purpose. 0:UART0, 1: UART1, <b>2:UART2</b>
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@note If CNVi solution is on the platform and UART0 is selected as BT Core interface,
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UART0 cannot be used for debug purpose.
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**/
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UINT32 DebugUartNumber : 2;
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UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug UART controller after post. 0: diabled, <b>1: enabled</b>
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/**
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<b>0: default pins</b>; 1: pins muxed with CNV_BRI/RGI
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UART0 can be configured to use two different sets of pins:
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This setting gives flexibility to use UART0 functionality on other pins when
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default ones are used for a different purpose.
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@note Since the second pin set contains pads which are also used for CNVi purpose, setting Uart0PinMuxing
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is exclusive with CNVi being enabled.
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**/
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UINT32 Uart0PinMuxing : 1;
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UINT32 RsvdBits0 : 28;
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} PCH_SERIAL_IO_CONFIG;
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#pragma pack (pop)
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#endif // _SERIAL_IO_CONFIG_H_
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