/** @file
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ME config block for PEI phase
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _ME_PEI_CONFIG_H_
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#define _ME_PEI_CONFIG_H_
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#include <ConfigBlock.h>
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#define ME_PEI_PREMEM_CONFIG_REVISION 2
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extern EFI_GUID gMePeiPreMemConfigGuid;
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#ifndef PLATFORM_POR
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#define PLATFORM_POR 0
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#endif
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#ifndef FORCE_ENABLE
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#define FORCE_ENABLE 1
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#endif
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#ifndef FORCE_DISABLE
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#define FORCE_DISABLE 2
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#endif
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#pragma pack (push,1)
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/**
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ME Pei Pre-Memory Configuration Structure.
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2</b>:
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- Change DidInitStat bit width.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: Enable</b> - HECI Send/Receive Timeouts.
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/**
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<b>(Test)</b>
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<b>0: Disabled</b>
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1: ME DID init stat 0 - Success
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2: ME DID init stat 1 - No Memory in Channels
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3: ME DID init stat 2 - Memory Init Error
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**/
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UINT32 DidInitStat : 2;
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/**
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<b>(Test)</b>
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<b>0: Set to 0 to enable polling for CPU replacement</b>
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1: Set to 1 will disable polling for CPU replacement
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**/
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UINT32 DisableCpuReplacedPolling : 1;
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UINT32 SendDidMsg : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable to send DID message.
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/**
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<b>(Test)</b>
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<b>0: Set to 0 to enable retry mechanism for HECI APIs</b>
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1: Set to 1 will disable retry mechanism for HECI APIs
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**/
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UINT32 DisableHeciRetry : 1;
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/**
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<b>(Test)</b>
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<b>0: ME BIOS will check each messages before sending</b>
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1: ME BIOS always sends messages without checking
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**/
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UINT32 DisableMessageCheck : 1;
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/**
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<b>(Test)</b>
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The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot
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in a MBP message. If set to 1, BIOS will send the MBP message with SkipMbp flag
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set causing CSME to respond with MKHI header only and no MBP data
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<b>0: ME BIOS will keep MBP and create HOB for MBP data</b>
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1: ME BIOS will skip MBP data
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**/
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UINT32 SkipMbpHob : 1;
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UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable HECI2.
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UINT32 KtDeviceEnable : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Kt Device.
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UINT32 RsvdBits : 22; ///< Reserved for future use & Config block alignment
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UINT32 Heci1BarAddress; ///< HECI1 BAR address.
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UINT32 Heci2BarAddress; ///< HECI2 BAR address.
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UINT32 Heci3BarAddress; ///< HECI3 BAR address.
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} ME_PEI_PREMEM_CONFIG;
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#pragma pack (pop)
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#define ME_PEI_CONFIG_REVISION 2
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extern EFI_GUID gMePeiConfigGuid;
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#pragma pack (push,1)
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/**
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ME Pei Post-Memory Configuration Structure.
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2</b>:
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- Add MctpBroadcastCycle test setting.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in PEI; <b>2: Send in DXE</b> - Send EOP at specific phase.
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/**
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HECI3 state from Mbp for reference in S3 path only
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<b>0: Disabled</b>; 1: Enabled
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**/
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UINT32 Heci3Enabled : 1;
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UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI.
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/**
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Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0.
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It will cause ME to unconfig if RTC is cleared.
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- 0: Disable
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- <b>1: Enable</b>
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- 2: Cmos is clear, status unkonwn
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- 3: Reserved
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**/
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UINT32 MeUnconfigOnRtcClear : 2;
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UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Program registers for MCTP Cycle.
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UINT32 RsvdBits : 25; ///< Reserved for future use & Config block alignment
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} ME_PEI_CONFIG;
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#pragma pack (pop)
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#endif // _ME_PEI_CONFIG_H_
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