/** @file
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Silicon Init APIs for MinPlatform BoardInitLib implementations.
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Guid/TcoWdtHob.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PmcLib.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchRegsPmc.h>
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/**
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Early Silicon initialization
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**/
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VOID
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EarlySiliconInit (
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VOID
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)
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{
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UINT16 Data16;
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UINT8 Data8;
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UINT8 TcoRebootHappened;
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TCO_WDT_HOB *TcoWdtHobPtr;
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EFI_STATUS Status;
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///
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/// LPC I/O Configuration
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///
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PchLpcIoDecodeRangesSet (
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(V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
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(V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
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(V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
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);
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PchLpcIoEnableDecodingSet (
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B_LPC_CFG_IOE_ME2 |
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B_LPC_CFG_IOE_SE |
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B_LPC_CFG_IOE_ME1 |
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B_LPC_CFG_IOE_KE |
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B_LPC_CFG_IOE_HGE |
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B_LPC_CFG_IOE_LGE |
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B_LPC_CFG_IOE_FDE |
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B_LPC_CFG_IOE_PPE |
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B_LPC_CFG_IOE_CBE |
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B_LPC_CFG_IOE_CAE
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);
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///
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/// Halt the TCO timer
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///
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Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);
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Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
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IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);
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///
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/// Read the Second TO status bit
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///
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Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
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if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
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TcoRebootHappened = 1;
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DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
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}
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else {
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TcoRebootHappened = 0;
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}
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///
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/// Create HOB
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///
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Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);
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if (!EFI_ERROR (Status)) {
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TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
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TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
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}
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///
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/// Clear the Second TO status bit
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///
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IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
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}
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/**
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Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
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**/
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VOID
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SiliconInit (
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VOID
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)
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{
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UINT16 ABase;
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ABase = PmcGetAcpiBase ();
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///
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/// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
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///
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IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
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IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
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}
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