/** @file
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Common USB policy shared between PCH and CPU
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Contains general features settings for xHCI and xDCI
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _USB_CONFIG_H_
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#define _USB_CONFIG_H_
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#define USB_CONFIG_REVISION 3
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extern EFI_GUID gUsbConfigGuid;
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#define MAX_USB2_PORTS 16
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#define MAX_USB3_PORTS 10
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#pragma pack (push,1)
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#define PCH_USB_OC_PINS_MAX 8 ///< Maximal possible number of USB Over Current pins
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///
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/// Overcurrent pins, the values match the setting of EDS, please refer to EDS for more details
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///
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typedef enum {
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UsbOverCurrentPin0 = 0,
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UsbOverCurrentPin1,
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UsbOverCurrentPin2,
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UsbOverCurrentPin3,
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UsbOverCurrentPin4,
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UsbOverCurrentPin5,
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UsbOverCurrentPin6,
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UsbOverCurrentPin7,
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UsbOverCurrentPinMax,
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UsbOverCurrentPinSkip = 0xFF
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} USB_OVERCURRENT_PIN;
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/**
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This structure configures per USB2 AFE settings.
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It allows to setup the port electrical parameters.
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**/
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typedef struct {
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/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
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000b - 0mV
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001b - 11.25mV
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010b - 16.9mV
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011b - 28.15mV
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100b - 28.15mV
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101b - 39.35mV
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110b - 45mV
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111b - 56.3mV
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**/
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UINT8 Petxiset;
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/** Per Port HS Transmitter Bias (PERPORTTXISET)
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000b - 0mV
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001b - 11.25mV
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010b - 16.9mV
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011b - 28.15mV
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100b - 28.15mV
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101b - 39.35mV
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110b - 45mV
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111b - 56.3mV
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**/
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UINT8 Txiset;
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/**
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Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
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00b - Emphasis OFF
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01b - De-emphasis ON
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10b - Pre-emphasis ON
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11b - Pre-emphasis & De-emphasis ON
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**/
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UINT8 Predeemp;
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/**
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Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
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1b - half-bit pre-emphasis
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0b - full-bit pre-emphasis
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**/
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UINT8 Pehalfbit;
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} USB20_AFE;
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/**
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This structure configures per USB2 port physical settings.
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It allows to setup the port location and port length, and configures the port strength accordingly.
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**/
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typedef struct {
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/**
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These members describe the specific over current pin number of USB 2.0 Port N.
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It is SW's responsibility to ensure that a given port's bit map is set only for
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one OC pin Description. USB2 and USB3 on the same combo Port must use the same
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OC pin (see: USB_OVERCURRENT_PIN).
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**/
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UINT32 OverCurrentPin : 8;
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 23; ///< Reserved bits
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/**
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Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating
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through Usb2PhySusPgEnable on PCH-LP
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**/
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USB20_AFE Afe; ///< USB2 AFE settings
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} USB20_PORT_CONFIG;
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/**
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This structure describes whether the USB3 Port N is enabled by platform modules.
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**/
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typedef struct {
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/**
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These members describe the specific over current pin number of USB 3.x Port N.
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It is SW's responsibility to ensure that a given port's bit map is set only for
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one OC pin Description. USB2 and USB3 on the same combo Port must use the same
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OC pin (see: USB_OVERCURRENT_PIN).
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**/
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UINT32 OverCurrentPin : 8;
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/**
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USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
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HSIO_TX_DWORD8[21:16]
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<b>Default = 00h</b>
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**/
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UINT32 HsioTxDownscaleAmp : 8;
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/**
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USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
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HSIO_TX_DWORD5[21:16]
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<b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
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**/
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UINT32 HsioTxDeEmph : 8;
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
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UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
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UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits0 : 5; ///< Reserved bits
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} USB30_PORT_CONFIG;
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/**
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The XDCI_CONFIG block describes the configurations
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of the xDCI Usb Device controller.
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**/
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typedef struct {
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/**
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This member describes whether or not the xDCI controller should be enabled.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 Enable : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} XDCI_CONFIG;
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//
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// Below defines are for proper UPD construction and values syncing between UPD and policy
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//
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#define B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN BIT0 ///< Enable the write to Signed Magnatude number added to the CTLE code bit
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#define B_XHCI_HSIO_FILTER_SELECT_N_EN BIT1 ///< Enable the write to LFPS filter select for n
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#define B_XHCI_HSIO_FILTER_SELECT_P_EN BIT2 ///< Enable the write to LFPS filter select for p
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#define B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN BIT3 ///< Enable the write to olfpscfgpullupdwnres
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#define N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG 3
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#define N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES 0
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#define N_XHCI_UPD_HSIO_FILTER_SELECT_P 0
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#define N_XHCI_UPD_HSIO_FILTER_SELECT_N 4
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typedef struct {
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/**
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Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_4_0)
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HSIO_RX_DWORD25 [20:16]
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Ex: -1 -- 1_0001. +1: 0_0001
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<b>Default = 0h</b>
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**/
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UINT32 HsioCtrlAdaptOffsetCfg : 5;
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/**
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LFPS filter select for n (filter_sel_n_2_0)
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HSIO_RX_DWORD51 [29:27]
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0h:1.6ns
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1h:2.4ns
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2h:3.2ns
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3h:4.0ns
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4h:4.8ns
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5h:5.6ns
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6h:6.4ns
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<b>Default = 0h</b>
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**/
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UINT32 HsioFilterSelN : 3;
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/**
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LFPS filter select for p (filter_sel_p_2_0)
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HSIO_RX_DWORD51 [26:24]
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0h:1.6ns
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1h:2.4ns
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2h:3.2ns
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3h:4.0ns
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4h:4.8ns
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5h:5.6ns
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6h:6.4ns
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<b>Default = 0h</b>
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**/
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UINT32 HsioFilterSelP : 3;
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/**
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Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
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HSIO_RX_DWORD51 [2:0]
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000 Prohibited
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001 45K
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010 Prohibited
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011 31K
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100 36K
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101 36K
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110 36K
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111 36K
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<b>Default = 3h</b>
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**/
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UINT32 HsioOlfpsCfgPullUpDwnRes : 3;
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UINT32 HsioCtrlAdaptOffsetCfgEnable : 1; ///< Enable the write to Signed Magnatude number added to the CTLE code, <b>0: Disable</b>; 1: Enable.
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UINT32 HsioFilterSelNEnable : 1; ///< Enable the write to LFPS filter select for n, <b>0: Disable</b>; 1: Enable.
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UINT32 HsioFilterSelPEnable : 1; ///< Enable the write to LFPS filter select for p, <b>0: Disable</b>; 1: Enable.
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UINT32 HsioOlfpsCfgPullUpDwnResEnable : 1; ///< Enable the write to olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits0 : 14; ///< Reserved bits
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} USB30_HSIO_RX_CONFIG;
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/**
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This member describes the expected configuration of the USB controller,
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Platform modules may need to refer Setup options, schematic, BIOS specification to update this field.
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The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring the schematic.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Added Usb2PhySusPgEnable - for enabling/disabling USB2 PHY SUS Well Power Gating
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<b>Revision 3</b>:
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Added HSIO Rx tuning policy options structure USB30_HSIO_RX_CONFIG
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This policy setting controls state of Compliance Mode enabling.
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Compliance Mode can be enabled for testing through this option but defualt setting is Disabled.
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<b>0:Disable</b>, 1: Enable
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**/
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UINT32 EnableComplianceMode : 1;
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/**
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This policy option when set will make BIOS program Port Disable Override register during PEI phase.
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When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming.
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If this is disabled, platform code MUST set it before booting into OS.
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<b>1: Enable</b>, 0: Disable
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**/
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UINT32 PdoProgramming : 1;
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/**
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This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
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Disabling this feature will disable overcurrent detection functionality.
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Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
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By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage.
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<b>1: Will program USB OC pin mapping in respective xHCI controller registers</b>
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0: Will clear OC pin mapping allow for OBS usage of OC pins
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**/
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UINT32 OverCurrentEnable : 1;
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/**
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<b>(Test)</b>
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If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be
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consumed by xHCI and OC mapping registers will be locked. OverCurrent mapping data is taken from respective port data
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structure from OverCurrentPin field.
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If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data.
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<b>1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data</b>
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0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.
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**/
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UINT32 XhciOcLock : 1;
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/**
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<b>(Test)</b>
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This policy option enables USB2 PHY SUS Well Power Gating functionality.
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Please note this is ignored on PCH H
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<b>0: disable USB2 PHY SUS Well Power Gating</b>
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1: enable USB2 PHY SUS Well Power Gating
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**/
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UINT32 Usb2PhySusPgEnable : 1;
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UINT32 RsvdBits0 : 27; ///< Reserved bits
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/**
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These members describe whether the USB2 Port N of PCH is enabled by platform modules.
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**/
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USB20_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
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/**
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These members describe whether the USB3 Port N of PCH is enabled by platform modules.
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**/
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USB30_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
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/**
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This member describes whether or not the xDCI controller should be enabled.
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**/
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XDCI_CONFIG XdciConfig;
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/**
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This member describes policy options for RX signal tuning in ModPHY
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**/
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USB30_HSIO_RX_CONFIG PortUsb30HsioRx[MAX_USB3_PORTS];
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} USB_CONFIG;
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#pragma pack (pop)
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#endif // _USB_CONFIG_H_
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