/** @file
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Si Config Block
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SI_CONFIG_H_
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#define _SI_CONFIG_H_
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#define SI_CONFIG_REVISION 3
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extern EFI_GUID gSiConfigGuid;
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#pragma pack (push,1)
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/**
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The Silicon Policy allows the platform code to publish a set of configuration
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information that the RC drivers will use to configure the silicon hardware.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Added TraceHubMemBase
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<b>Revision 3</b>
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- Deprecated SkipPostBootSai
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
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//
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// Platform specific common policies that used by several silicon components.
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//
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UINT32 CsmFlag : 1; ///< Offset 44 BIT0: CSM status flag.
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/**
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@deprecated since revision 3
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**/
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UINT32 SkipPostBootSai : 1;
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UINT32 RsvdBits : 30; ///< Reserved
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UINT32 *SsidTablePtr; // Offset 48
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UINT16 NumberOfSsidTableEntry; // Offset 52
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UINT16 Reserved; // Offset 54
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/**
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If Trace Hub is enabled and trace to memory is desired, Platform code or BootLoader needs to allocate trace hub memory
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as reserved, and save allocated memory base to TraceHubMemBase to ensure Trace Hub memory is configured properly.
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To get total trace hub memory size please refer to TraceHubCalculateTotalBufferSize ()
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Noted: If EDKII memory service is used to allocate memory, it will require double memory size to support size-aligned memory allocation,
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so Platform code or FSP Wrapper code should ensure enough memory available for size-aligned TraceHub memory allocation.
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**/
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UINT32 TraceHubMemBase; // Offset 58
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} SI_CONFIG;
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#pragma pack (pop)
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#define DEFAULT_SSVID 0x8086
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#define DEFAULT_SSDID 0x7270
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#define MAX_DEVICE_COUNT 70
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///
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/// Subsystem Vendor ID / Subsystem ID
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///
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typedef struct {
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UINT16 SubSystemVendorId;
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UINT16 SubSystemId;
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} SVID_SID_VALUE;
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//
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// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
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//
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typedef struct {
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union {
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struct {
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UINT64 Register:12;
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UINT64 Function:3;
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UINT64 Device:5;
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UINT64 Bus:8;
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UINT64 Reserved1:4;
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UINT64 Segment:16;
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UINT64 Reserved2:16;
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} Bits;
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UINT64 SegBusDevFuncRegister;
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} Address;
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SVID_SID_VALUE SvidSidValue;
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UINT32 Reserved;
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} SVID_SID_INIT_ENTRY;
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#endif // _SI_CONFIG_H_
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