/** @file
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This file is PeiCpuPolicyLibPreMem library.
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Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiCpuPolicyLibrary.h"
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#include <Library/PciSegmentLib.h>
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#include <Library/PostCodeLib.h>
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#include <Library/SaPlatformLib.h>
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadCpuSecurityPreMemConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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}
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/**
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Load Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadCpuConfigLibPreMemConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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CPU_GENERATION CpuGeneration;
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CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
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CPU_FAMILY CpuFamily;
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CPU_SKU CpuSku;
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BOOLEAN PegDisabled;
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UINT64 MchBar;
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UINT64 SaPciBase;
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CpuConfigLibPreMemConfig = ConfigBlockPointer;
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CpuFamily = GetCpuFamily();
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CpuSku = GetCpuSku();
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DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Name = %g\n", &CpuConfigLibPreMemConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuConfigLibPreMemConfig->Header.GuidHob.Header.HobLength));
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/********************************
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CPU Config Lib PreMem configuration
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********************************/
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CpuConfigLibPreMemConfig->HyperThreading = CPU_FEATURE_ENABLE;
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CpuConfigLibPreMemConfig->BootFrequency = 1; // Maximum non-turbo Performance
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CpuConfigLibPreMemConfig->ActiveCoreCount = 0; // All cores active
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CpuConfigLibPreMemConfig->JtagC10PowerGateDisable = CPU_FEATURE_DISABLE;
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CpuConfigLibPreMemConfig->BistOnReset = CPU_FEATURE_DISABLE;
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CpuConfigLibPreMemConfig->VmxEnable = CPU_FEATURE_ENABLE;
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CpuConfigLibPreMemConfig->CpuRatio = (RShiftU64 (AsmReadMsr64 (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK);
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CpuGeneration = GetCpuGeneration();
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if(CpuGeneration == EnumCflCpu){
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///
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/// FCLK Frequency
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///
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SaPciBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, 0);
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PciSegmentReadBuffer (SaPciBase + R_SA_MCHBAR, sizeof (MchBar), &MchBar);
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MchBar &= ((UINT64) ~BIT0);
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if (IsPchLinkDmi (CpuFamily) && (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG0_FUN_NUM, PCI_VENDOR_ID_OFFSET)) != 0xFFFF)) {
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PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3;
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} else {
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PegDisabled = 1;
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}
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///
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/// DT/Halo FCLK = 1GHz
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/// Ulx/Ult FCLK = 800MHz
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///
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if (((CpuSku == EnumCpuHalo) && (!PegDisabled)) || (CpuSku == EnumCpuTrad)) {
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CpuConfigLibPreMemConfig->FClkFrequency = 1; // 1Ghz
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}
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else {
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CpuConfigLibPreMemConfig->FClkFrequency = 0; // 800MHz
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}
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///
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/// Disable Peci Reset on C10 exit on CFL based CPU's
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/// Setting to 1 will activate the message that disables peci reset.
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///
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CpuConfigLibPreMemConfig->PeciC10Reset = 1;
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}
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}
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/**
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Load Overclocking pre-mem Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadCpuOverclockingPreMemConfigDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig;
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CpuOverclockingPreMemConfig = ConfigBlockPointer;
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/********************************
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CPU Overclocking PreMem configuration
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********************************/
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DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Name = %g\n", &CpuOverclockingPreMemConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuOverclockingPreMemConfig->Header.GuidHob.Header.HobLength));
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}
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static COMPONENT_BLOCK_ENTRY mCpuIpBlocksPreMem [] = {
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{&gCpuConfigLibPreMemConfigGuid, sizeof (CPU_CONFIG_LIB_PREMEM_CONFIG), CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION, LoadCpuConfigLibPreMemConfigDefault},
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{&gCpuOverclockingPreMemConfigGuid, sizeof (CPU_OVERCLOCKING_PREMEM_CONFIG), CPU_OVERCLOCKING_CONFIG_REVISION, LoadCpuOverclockingPreMemConfigDefault},
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};
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/**
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Get CPU PREMEM config block table total size.
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@retval Size of CPU PREMEM config block table
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**/
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UINT16
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EFIAPI
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CpuGetPreMemConfigBlockTotalSize (
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VOID
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)
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{
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return GetComponentConfigBlockTotalSize (&mCpuIpBlocksPreMem[0], sizeof (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY));
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}
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/**
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CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks.
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@param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM config blocks
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@retval EFI_SUCCESS The policy default is initialized.
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@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
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**/
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EFI_STATUS
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EFIAPI
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CpuAddPreMemConfigBlocks (
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IN VOID *ConfigBlockTableAddress
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)
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{
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EFI_STATUS Status;
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DEBUG((DEBUG_INFO, "CPU Pre-Mem Entry \n"));
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PostCode (0xC00);
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Status = AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlocksPreMem[0], sizeof (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY));
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DEBUG((DEBUG_INFO, "CpuAddPreMemConfigBlocks Done \n"));
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PostCode (0xC0F);
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return Status;
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}
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