/** @file
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CPU Overclocking Config Block.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_OVERCLOCKING_PREMEM_CONFIG_H_
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#define _CPU_OVERCLOCKING_PREMEM_CONFIG_H_
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#define CPU_OVERCLOCKING_CONFIG_REVISION 4
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extern EFI_GUID gCpuOverclockingPreMemConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Overclocking Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>
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- Deprecate RingMinOcRatio
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<b>Revision 3</b>
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- Change RingDownBin default to 'Enabled'
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<b>Revision 4</b>
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- Add TvbRatioClipping, TvbVoltageOptimization
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Overclocking support. This controls whether OC mailbox transactions are sent.
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If disabled, all policies in this config block besides OcSupport and OcLock will be ignored.
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<b>0: Disable</b>;
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1: Enable.
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@note If PcdOverclockEnable is disabled, this should also be disabled.
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**/
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UINT32 OcSupport : 1;
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UINT32 OcLock : 1; ///< If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; <b>0: Disable</b>; 1: Enable (Lock).
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/**
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Core voltage mode, specifies which voltage mode the processor will be operating.
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<b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
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1: Override, sets one voltage for for the entire frequency range, Pn-P0.
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**/
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UINT32 CoreVoltageMode : 1;
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UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
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UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX3 ratio to maximize possible ratio for SSE workload.
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UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
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/**
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Ring Downbin enable/disable.
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When enabled, the CPU will force the ring ratio to be lower than the core ratio.
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Disabling will allow the ring and core ratios to run at the same frequency.
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Uses OC Mailbox command 0x19.
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0: Disables Ring Downbin feature. <b>1: Enables Ring downbin feature.</b>
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**/
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UINT32 RingDownBin : 1;
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/**
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Ring voltage mode, specifies which voltage mode the processor will be operating.
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<b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
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1: Override, sets one voltage for for the entire frequency range, Pn-P0.
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**/
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UINT32 RingVoltageMode : 1;
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UINT32 RsvdBits : 10; ///< Reserved for future use
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/**
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Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
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<b>0. no override/HW defaults.</b>. Range 0-255. Max range varies by CPU sku.
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**/
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UINT8 CoreMaxOcRatio;
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/**
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The core voltage override which is applied to the entire range of cpu core frequencies.
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Used when CoreVoltageMode = Override.
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<b>0. no override</b>. Range 0-2000 mV.
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**/
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UINT16 CoreVoltageOverride;
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/**
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Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.
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Used when CoreVoltageMode = Adaptive.
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<b>0. no override</b>. Range 0-2000mV.
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**/
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UINT16 CoreVoltageAdaptive;
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/**
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The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
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This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
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**/
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INT16 CoreVoltageOffset;
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/**
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Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.
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<b>0. no override/HW defaults.</b>. Range 0-255. Max range varies by CPU sku.
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**/
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UINT8 RingMaxOcRatio;
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/**
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The ring voltage override which is applied to the entire range of cpu ring frequencies.
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Used when RingVoltageMode = Override.
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<b>0. no override</b>. Range 0-2000 mV.
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**/
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UINT16 RingVoltageOverride;
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/**
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Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range.
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Used when RingVoltageMode = Adaptive.
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<b>0. no override</b>. Range 0-2000mV.
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**/
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UINT16 RingVoltageAdaptive;
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/**
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The ring voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
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This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
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**/
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INT16 RingVoltageOffset;
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UINT8 RingMinOcRatio; ///< Deprecated since rev 2. Minimum ring ratio override. <b>0: Hardware defaults.</b> Range: 0-83.
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UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 McPllVoltageOffset : 6; ///< Memory Controller PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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/**
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This service controls Core frequency reduction caused by high package temperatures for processors that
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implement the Intel Thermal Velocity Boost (TVB) feature. It is required to be disabled for supporting
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overclocking at frequencies higher than the default max turbo frequency.
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<b>0: Disables TVB ratio clipping. </b>1: Enables TVB ratio clipping.
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**/
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UINT32 TvbRatioClipping : 1;
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/**
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This service controls thermal based voltage optimizations for processors that implement the Intel
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Thermal Velocity Boost (TVB) feature.
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0: Disables TVB voltage optimization. <b>1: Enables TVB voltage optimization.</b>
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**/
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UINT32 TvbVoltageOptimization : 1;
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UINT32 RsvdBits1 : 6;
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/**
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TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius.
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<b> Default: 0 Hardware Defaults </b> Range 0 to 63.
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**/
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UINT8 TjMaxOffset;
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} CPU_OVERCLOCKING_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_OVERCLOCKING_CONFIG_H_
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