/** @file
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CPU Config Block.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_CONFIG_H_
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#define _CPU_CONFIG_H_
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#define CPU_CONFIG_REVISION 3
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extern EFI_GUID gCpuConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig.
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<b>Revision 3</b>:
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- Move DebugInterfaceEnable from CPU_TEST_CONFIG.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Enable or Disable Advanced Encryption Standard (AES) feature.
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For some countries, this should be disabled for legal reasons.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 AesEnable : 1;
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UINT32 SkipMpInit : 1; ///< @deprecated since revision 2. For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
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UINT32 DebugInterfaceEnable : 1; ///< Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits : 28; ///< Reserved for future use
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EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
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} CPU_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_CONFIG_H_
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