/** @file
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*
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* Copyright (c) 2018, Linaro Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __HI3660_H__
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#define __HI3660_H__
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#define HKADC_SSI_REG_BASE 0xE82B8000
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#define PCTRL_REG_BASE 0xE8A09000
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#define PCTRL_CTRL3 (PCTRL_REG_BASE + 0x010)
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#define PCTRL_CTRL24 (PCTRL_REG_BASE + 0x064)
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#define PCTRL_CTRL3_USB_TXCO_EN (1 << 1)
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#define PCTRL_CTRL24_USB3PHY_3MUX1_SEL (1 << 25)
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#define SCTRL_REG_BASE 0xFFF0A000
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#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120)
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#define SCTRL_SCFPLLCTRL0_FPLL0_EN (1 << 0)
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#define SCTRL_BAK_DATA0 (SCTRL_REG_BASE + 0x40C)
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#define USB3OTG_BC_REG_BASE 0xFF200000
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#define USB3OTG_CTRL0 (USB3OTG_BC_REG_BASE + 0x000)
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#define USB3OTG_CTRL2 (USB3OTG_BC_REG_BASE + 0x008)
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#define USB3OTG_CTRL3 (USB3OTG_BC_REG_BASE + 0x00C)
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#define USB3OTG_CTRL4 (USB3OTG_BC_REG_BASE + 0x010)
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#define USB3OTG_CTRL6 (USB3OTG_BC_REG_BASE + 0x018)
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#define USB3OTG_CTRL7 (USB3OTG_BC_REG_BASE + 0x01C)
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#define USB3OTG_PHY_CR_STS (USB3OTG_BC_REG_BASE + 0x050)
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#define USB3OTG_PHY_CR_CTRL (USB3OTG_BC_REG_BASE + 0x054)
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#define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN (1 << 15)
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#define USB3OTG_CTRL2_TEST_POWERDOWN_SSP (1 << 1)
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#define USB3OTG_CTRL2_TEST_POWERDOWN_HSP (1 << 0)
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#define USB3OTG_CTRL3_VBUSVLDEXT (1 << 6)
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#define USB3OTG_CTRL3_VBUSVLDEXTSEL (1 << 5)
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#define USB3OTG_CTRL7_REF_SSP_EN (1 << 16)
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#define USB3OTG_PHY_CR_DATA_OUT(x) (((x) & 0xFFFF) << 1)
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#define USB3OTG_PHY_CR_ACK (1 << 0)
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#define USB3OTG_PHY_CR_DATA_IN(x) (((x) & 0xFFFF) << 4)
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#define USB3OTG_PHY_CR_WRITE (1 << 3)
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#define USB3OTG_PHY_CR_READ (1 << 2)
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#define USB3OTG_PHY_CR_CAP_DATA (1 << 1)
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#define USB3OTG_PHY_CR_CAP_ADDR (1 << 0)
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#define PMU_REG_BASE 0xFFF34000
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#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x06b << 2))
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#define LDO9_VSET_MASK (7 << 0)
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#define PMIC_LDO16_ONOFF_ECO_REG (PMU_REG_BASE + (0x078 << 2))
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#define LDO16_ONOFF_ECO_LDO16_ENABLE BIT1
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#define LDO16_ONOFF_ECO_ECO_ENABLE BIT0
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#define PMIC_LDO16_VSET_REG (PMU_REG_BASE + (0x079 << 2))
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#define LDO16_VSET_MASK (7 << 0)
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#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2))
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#define PMIC_OSC32K_ONOFF_CTRL (PMU_REG_BASE + (0x0CC << 2))
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#define PMIC_HARDWARE_CTRL0_WIFI_CLK (1 << 5)
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#define PMIC_OSC32K_ONOFF_CTRL_EN_32K (1 << 1)
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#define CRG_REG_BASE 0xFFF35000
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#define CRG_PEREN0 (CRG_REG_BASE + 0x000)
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#define CRG_PEREN2 (CRG_REG_BASE + 0x020)
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#define CRG_PERDIS2 (CRG_REG_BASE + 0x024)
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#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028)
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#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C)
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#define CRG_PEREN4 (CRG_REG_BASE + 0x040)
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#define CRG_PERDIS4 (CRG_REG_BASE + 0x044)
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#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048)
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#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C)
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#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078)
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#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C)
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#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080)
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#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084)
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#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088)
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#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C)
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#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090)
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#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094)
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#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098)
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#define CRG_CLKDIV4 (CRG_REG_BASE + 0x0B8)
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#define CRG_ISOEN (CRG_REG_BASE + 0x144)
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#define CRG_ISODIS (CRG_REG_BASE + 0x148)
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#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C)
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#define PERI_UFS_BIT (1 << 12)
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#define PERI_ARST_UFS_BIT (1 << 7)
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#define PEREN0_GT_HCLK_SD BIT30
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#define PEREN2_HKADCSSI BIT24
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#define PEREN4_GT_CLK_SD BIT17
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#define PEREN4_GT_ACLK_USB3OTG (1 << 1)
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#define PEREN4_GT_CLK_USB3OTG_REF (1 << 0)
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#define PERRSTEN2_HKADCSSI BIT24
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#define PERRSTEN4_SD BIT18
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#define PERRSTEN4_USB3OTG_MUX (1 << 8)
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#define PERRSTEN4_USB3OTG_AHBIF (1 << 7)
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#define PERRSTEN4_USB3OTG_32K (1 << 6)
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#define PERRSTEN4_USB3OTG (1 << 5)
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#define PERRSTEN4_USB3OTGPHY_POR (1 << 3)
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#define PERISOEN_USB_REFCLK_ISO_EN (1 << 25)
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#define CLKDIV4_SC_SEL_SD_MASK (7 << 4)
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#define CLKDIV4_SC_DIV_SD_MASK 0xf
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#define CLKDIV4_SC_MASK_SHIFT 16
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#define CLKDIV4_SC_SEL_SD(x) (((x) & 0x7) << 4)
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#define CLKDIV4_SC_DIV_SD(x) ((x) & 0xf)
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#define CRG_CLKDIV16_OFFSET 0x0E8
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#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9)
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#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9)
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#define CRG_CLKDIV17_OFFSET 0x0EC
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#define SC_DIV_UFS_PERIBUS (1 << 14)
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#define IOMG_MMC0_REG_BASE 0xFF37E000
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#define IOMG_MMC0_000_REG (IOMG_MMC0_REG_BASE + 0x000)
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#define IOMG_MMC0_001_REG (IOMG_MMC0_REG_BASE + 0x004)
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#define IOMG_MMC0_002_REG (IOMG_MMC0_REG_BASE + 0x008)
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#define IOMG_MMC0_003_REG (IOMG_MMC0_REG_BASE + 0x00C)
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#define IOMG_MMC0_004_REG (IOMG_MMC0_REG_BASE + 0x010)
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#define IOMG_MMC0_005_REG (IOMG_MMC0_REG_BASE + 0x014)
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#define IOCG_MMC0_REG_BASE 0xFF37E800
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#define IOCG_MMC0_000_REG (IOCG_MMC0_REG_BASE + 0x000)
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#define IOCG_MMC0_001_REG (IOCG_MMC0_REG_BASE + 0x004)
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#define IOCG_MMC0_002_REG (IOCG_MMC0_REG_BASE + 0x008)
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#define IOCG_MMC0_003_REG (IOCG_MMC0_REG_BASE + 0x00C)
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#define IOCG_MMC0_004_REG (IOCG_MMC0_REG_BASE + 0x010)
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#define IOCG_MMC0_005_REG (IOCG_MMC0_REG_BASE + 0x014)
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#define IOMG_AO_REG_BASE 0xFFF11000
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#define IOMG_AO_006_REG (IOMG_AO_REG_BASE + 0x018)
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#define IOMG_FUNC0 0
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#define IOMG_FUNC1 1
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#define IOCG_PULLUP BIT0
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#define IOCG_PULLDOWN BIT1
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#define IOCG_DRIVE(x) ((x) << 4)
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#define UFS_SYS_REG_BASE 0xFF3B1000
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#define UFS_SYS_PSW_POWER_CTRL_OFFSET 0x004
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#define UFS_SYS_PHY_ISO_EN_OFFSET 0x008
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#define UFS_SYS_HC_LP_CTRL_OFFSET 0x00C
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#define UFS_SYS_PHY_CLK_CTRL_OFFSET 0x010
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#define UFS_SYS_PSW_CLK_CTRL_OFFSET 0x014
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#define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET 0x018
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#define UFS_SYS_RESET_CTRL_EN_OFFSET 0x01C
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#define UFS_SYS_MONITOR_HH_OFFSET 0x03C
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#define UFS_SYS_UFS_SYSCTRL_OFFSET 0x05C
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#define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET 0x060
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#define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET 0x064
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#define BIT_UFS_PSW_ISO_CTRL (1 << 16)
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#define BIT_UFS_PSW_MTCMOS_EN (1 << 0)
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#define BIT_UFS_REFCLK_ISO_EN (1 << 16)
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#define BIT_UFS_PHY_ISO_CTRL (1 << 0)
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#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16)
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#define BIT_SYSCTRL_PWR_READY (1 << 8)
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#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24)
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#define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8)
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#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF)
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#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4)
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#define MASK_UFS_CLK_GATE_BYPASS (0x3F)
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#define BIT_SYSCTRL_LP_RESET_N (1 << 0)
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#define BIT_UFS_REFCLK_SRC_SE1 (1 << 0)
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#define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16)
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#define MASK_UFS_DEVICE_RESET (1 << 16)
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#define BIT_UFS_DEVICE_RESET (1 << 0)
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#endif /* __HI3660_H__ */
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