/** @file
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*
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* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2018, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Uefi.h>
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#include <IndustryStandard/Acpi.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/OemMiscLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciExpressLib.h>
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#include <Library/PlatformPciLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciPlatform.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Regs/HisiPcieV1RegOffset.h>
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#define INVALID_CAPABILITY_00 0x00
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#define INVALID_CAPABILITY_FF 0xFF
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#define PCI_CAPABILITY_POINTER_MASK 0xFC
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STATIC
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UINT64
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GetPcieCfgAddress (
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UINT64 Ecam,
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UINTN Bus,
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UINTN Device,
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UINTN Function,
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UINTN Reg
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)
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{
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return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg);
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}
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STATIC
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE *
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GetAppetureByRootBridgeIo (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridge
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)
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{
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EFI_STATUS Status;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration = NULL;
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UINTN Hb;
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UINTN Rb;
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Status = RootBridge->Configuration (
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RootBridge,
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(VOID **)&Configuration
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] RootBridgeIo->Configuration failed %r\n",
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__FUNCTION__, __LINE__, Status));
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return NULL;
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};
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while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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if (Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
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break;
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}
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Configuration++;
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}
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if (Configuration->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find bus descriptor\n", __FUNCTION__, __LINE__));
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return NULL;
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}
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for (Hb = 0; Hb < PCIE_MAX_HOSTBRIDGE; Hb++) {
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for (Rb = 0; Rb < PCIE_MAX_ROOTBRIDGE; Rb++) {
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if (RootBridge->SegmentNumber == mResAppeture[Hb][Rb].Segment &&
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Configuration->AddrRangeMin >= mResAppeture[Hb][Rb].BusBase &&
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Configuration->AddrRangeMax <= mResAppeture[Hb][Rb].BusLimit) {
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return &mResAppeture[Hb][Rb];
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}
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}
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}
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DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find PCI appeture\n", __FUNCTION__, __LINE__));
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return NULL;
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}
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STATIC
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VOID
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SetAtuConfig0RW (
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private,
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UINT32 Index
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)
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{
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UINTN RbPciBase = Private->RbPciBar;
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UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
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UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
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{
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UINTN i;
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for (i=0; i<0x20; i+=4) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
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}
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}
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}
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STATIC
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VOID
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SetAtuConfig1RW (
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private,
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UINT32 Index
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)
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{
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UINTN RbPciBase = Private->RbPciBar;
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UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
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UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
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{
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UINTN i;
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for (i=0; i<0x20; i+=4) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
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}
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}
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}
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STATIC
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VOID
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SetAtuIoRW (UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
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{
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
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{
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UINTN i;
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for (i=0; i<0x20; i+=4) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
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}
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}
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}
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STATIC
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VOID
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SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
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{
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
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{
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UINTN i;
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for (i=0; i<0x20; i+=4) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
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}
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}
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}
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VOID
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InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private)
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{
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SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
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SetAtuConfig0RW (Private, 1);
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SetAtuConfig1RW (Private, 2);
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SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
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}
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/*++
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Routine Description:
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Perform Platform initialization first in PciPlatform.
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Arguments:
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Returns:
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VOID.
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--*/
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VOID
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EFIAPI
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PciInitPlatform (
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VOID
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)
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{
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UINT32 Port;
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UINT32 HostBridgeNum = 0;
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for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
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for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
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InitAtu (&mResAppeture[HostBridgeNum][Port]);
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}
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}
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return;
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}
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STATIC
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BOOLEAN
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PcieCheckAriFwdEn (
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UINTN PciBaseAddr
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)
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{
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UINT8 PciPrimaryStatus;
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UINT8 CapabilityOffset;
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UINT8 CapId;
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UINT8 TempData;
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PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET);
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if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) {
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CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET);
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CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
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while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) {
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CapId = MmioRead8 (PciBaseAddr + CapabilityOffset);
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if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) {
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break;
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}
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CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1);
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CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
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}
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} else {
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return FALSE;
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}
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if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) {
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return FALSE;
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}
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TempData = MmioRead16 (PciBaseAddr + CapabilityOffset +
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EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET);
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TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING;
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if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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VOID
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EnlargeAtuConfig0 (
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IN EFI_HANDLE HostBridge
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)
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{
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc = NULL;
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EFI_STATUS Status;
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EFI_HANDLE RootBridgeHandle = NULL;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo = NULL;
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture;
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UINTN RbPciBase;
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UINT64 MemLimit;
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DEBUG ((DEBUG_INFO, "In Enlarge RP iATU Config 0.\n"));
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Status = gBS->HandleProtocol (
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HostBridge,
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&gEfiPciHostBridgeResourceAllocationProtocolGuid,
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(VOID **)&ResAlloc
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __FUNCTION__,
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__LINE__, Status));
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return;
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}
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while (TRUE) {
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Status = ResAlloc->GetNextRootBridge (
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ResAlloc,
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&RootBridgeHandle
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);
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if (EFI_ERROR (Status)) {
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break;
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}
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Status = gBS->HandleProtocol (
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RootBridgeHandle,
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&gEfiPciRootBridgeIoProtocolGuid,
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(VOID **)&RootBridgeIo
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
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// This should never happen so that it is a fatal error and we don't try
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// to continue
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break;
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}
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Appeture = GetAppetureByRootBridgeIo (RootBridgeIo);
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if (Appeture == NULL) {
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DEBUG ((DEBUG_ERROR, "[%a:%d] Get appeture failed\n", __FUNCTION__,
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__LINE__));
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continue;
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}
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RbPciBase = Appeture->RbPciBar;
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// Those ARI FWD Enable Root Bridge, need enlarge iATU window.
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if (PcieCheckAriFwdEn (RbPciBase)) {
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MemLimit = GetPcieCfgAddress (Appeture->Ecam, Appeture->BusBase + 2, 0, 0, 0) - 1;
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1);
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MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
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}
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}
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}
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/*++
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Routine Description:
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Perform Platform initialization by the phase indicated.
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Arguments:
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HostBridge - The associated PCI host bridge handle.
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Phase - The phase of the PCI controller enumeration.
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ChipsetPhase - Defines the execution phase of the PCI chipset driver.
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Returns:
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--*/
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VOID
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EFIAPI
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PhaseNotifyPlatform (
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IN EFI_HANDLE HostBridge,
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
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IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
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)
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{
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switch (Phase) {
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case EfiPciHostBridgeEndEnumeration:
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// Only do once
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if (ChipsetPhase == ChipsetEntry) {
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DEBUG ((DEBUG_INFO, "PCI end enumeration platform hook\n"));
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EnlargeAtuConfig0 (HostBridge);
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}
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break;
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default:
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break;
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}
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return ;
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}
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