/** @file
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*
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* Copyright (c) 2020, Pete Batard <pete@akeo.ie>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <IndustryStandard/Bcm2836.h>
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#ifndef __BCM2836_GPU_H__
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#define __BCM2836_GPU_H__
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/* VideoCore constants */
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#define BCM2836_VCHIQ_OFFSET 0x0000B840
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#define BCM2836_VCHIQ_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_VCHIQ_OFFSET)
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#define BCM2836_VCHIQ_LENGTH 0x00000010
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#define BCM2836_V3D_BUS_OFFSET 0x00C00000
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#define BCM2836_V3D_BUS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_V3D_BUS_OFFSET)
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#define BCM2836_V3D_BUS_LENGTH 0x00001000
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#define BCM2836_HVS_OFFSET 0x00400000
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#define BCM2836_HVS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HVS_OFFSET)
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#define BCM2836_HVS_LENGTH 0x00006000
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#define BCM2836_PV0_OFFSET 0x00206000
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#define BCM2836_PV0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV0_OFFSET)
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#define BCM2836_PV0_LENGTH 0x00000100
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#define BCM2836_PV1_OFFSET 0x00207000
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#define BCM2836_PV1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV1_OFFSET)
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#define BCM2836_PV1_LENGTH 0x00000100
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#define BCM2836_PV2_OFFSET 0x00807000
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#define BCM2836_PV2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV2_OFFSET)
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#define BCM2836_PV2_LENGTH 0x00000100
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#define BCM2836_HDMI0_OFFSET 0x00902000
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#define BCM2836_HDMI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI0_OFFSET)
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#define BCM2836_HDMI0_LENGTH 0x00000600
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#define BCM2836_HDMI1_OFFSET 0x00808000
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#define BCM2836_HDMI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI1_OFFSET)
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#define BCM2836_HDMI1_LENGTH 0x00000100
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#endif /* __BCM2836_MISC_H__ */
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