/** @file
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*
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* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <NeoverseN1Soc.h>
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// The total number of descriptors, including the final "end-of-table" descriptor.
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13
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/**
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Returns the Virtual Memory Map of the platform.
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
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on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
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a Physical-to-Virtual Memory mapping. This array
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must be ended by a zero-filled entry.
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
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)
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{
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UINTN Index = 0;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
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NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
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UINT64 DramBlock2Size;
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PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
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DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
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NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
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(UINT64)SIZE_1GB);
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ResourceAttributes =
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED;
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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ResourceAttributes,
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FixedPcdGet64 (PcdDramBlock2Base),
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DramBlock2Size);
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ASSERT (VirtualMemoryMap != NULL);
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Index = 0;
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VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
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MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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if (VirtualMemoryTable == NULL) {
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return;
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}
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// SubSystem Peripherals - Generic Watchdog
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VirtualMemoryTable[Index].PhysicalBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE;
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VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE;
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GENERIC_WDOG_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SubSystem Peripherals - GIC-600
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VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GIC_BASE;
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VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GIC_BASE;
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GIC_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SubSystem Peripherals - GICR-600
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VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GICR_BASE;
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VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GICR_BASE;
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GICR_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// OnChip non-secure SRAM
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VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE;
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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// PCIe RC Configuration Space
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieRootPortConfigBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieRootPortConfigBaseAddress);
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VirtualMemoryTable[Index].Length = PcdGet32 (PcdPcieRootPortConfigBaseSize);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIe ECAM Configuration Space
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress);
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VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
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FixedPcdGet32 (PcdPcieBusMin) + 1) *
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SIZE_1MB;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIe MMIO32 Memory Space
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieMmio32Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieMmio32Base);
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VirtualMemoryTable[Index].Length = PcdGet32 (PcdPcieMmio32Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIe MMIO64 Memory Space
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieMmio64Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieMmio64Base);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SubSystem Pheripherals - UART0
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VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE;
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VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE;
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_UART0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// DDR Primary (2GB)
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
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// DDR Secondary
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base);
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VirtualMemoryTable[Index].Length = DramBlock2Size;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
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// Expansion Peripherals
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VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0;
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VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0;
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n"));
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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